• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.1
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• pp.90-97
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• 2014

In this paper, we have designed the antenna for Korea SAT-5 Satellite Communication which can use Ka band in the earth station. The antenna structure consist of the the dual-offset gregorian reflector that has high gain and efficiency, the corrugated horn that has symmetric radiation patterns and low side lobe levels, the iris polarizer that make circular polarization and the OrthoMode Transducer that separate transmitting and receiving signals. The designed antenna gain is more than 45.7dBi in Tx-band which use LHCP and 42.0dBi in Rx-band which use RHCP. The co-polarized and cross-polarized radiation pattern comply with ITU-R S.580-6 and S.731-1 that are recommended by International Telecommunication Union in the geostationary satellite. The Axial ratio is less than 1.0dB in Tx-band and 1.5dB in Rx-band that meet MIL-STD-188-164A.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.3
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• pp.30-39
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• 2011

In this note, a systematic design of a new robust nonlinear continuous variable structure control system(VSCS) based on the modified state dependent nonlinear form is presented for the control of uncertain affine nonlinear systems with mismatched uncertainties and matched disturbance. After an affine uncertain nonlinear system is represented in the form of state dependent nonlinear system, a systematic design of a new robust nonlinear VSCS is presented. The uncertainty of the nonlinear system function is separated into the tow parts, i.e., state dependent term and state independent term for extension of target plants. To be linear in the closed loop resultant dynamics and in order to easily satisfy the existence condition of the sliding mode, the transformed linear sliding surface is applied. A corresponding control input is proposed to satisfy the closed loop exponential stability and the existence condition of the sliding mode on the linear transformed sliding surface, which will be investigated in Theorem 1. For practical application, the discontinuity of the control input as the inherent property of the VSS is improved dramatically. Through a design example and simulation studies, the usefulness of the proposed controller is verified.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.6
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• pp.699-706
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• 2015

A previous adapter have a single-ouput, however, a demand of a multi-output adapter increase in the recent industrial site. In order to satisfy the demand, in this research, we implement a programmable high efficiency multi-output adapter. The basic structure of the adapter introduced in this paper is a sort of flyback. The way for producing the reference voltage of the adapter proposed is similar to the way in the general flyback implemented with TL431. In addition to the basic concept of the design, however, we introduce a digital variable resistor, AD5246BKSZ10-RL7 and a microcontroller for changing a programmable multi-output. It makes output be variable that the digital variable resistor change the reference voltage of the adapter by order of the microcontroller. The adapter output voltage is controllable in the range of 20V by the user, and the power efficiency is proven to be 85%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.2
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• pp.302-312
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• 2012

In this paper, small-area and high-reliability design techniques of a 512-bit EEPROM are designed for UHF RFID tag chips. For a small-area technique, there are a WL driver circuit simplifying its decoding logic and a VREF generator using a resistor divider instead of a BGR. The layout size of the designed 512-bit EEPROM IP with MagnaChip's $0.18{\mu}m$ EEPROM is $59.465{\mu}m{\times}366.76{\mu}m$ which is 16.7% smaller than the conventional counterpart. Also, we solve a problem of breaking 5V devices by keeping VDDP voltage constant since a boosted output from a DC-DC converter is made discharge to the common ground VSS instead of VDDP (=3.15V) in getting out of the write mode.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.5
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• pp.400-408
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• 2007

In this paper, development of the 8kW parallel module converter is presented. For a effective configuration of FB-PWM converter, this paper proposes 4-parallel operation of 2 kw-module. FB converter of 2-kW module is controlled by phase shut PWM and in order to achieve ZVZCS, the simple auxiliary circuit is applied in secondary side. In order to achieve ZCS, control logic for auxiliary circuit operation is designed to reset the primary current during free-wheeling period. For output current sharing of 4-modules, the charge control is employed. The charge control logic is designed with phase shift PWM logic. Voltage controller is implemented by using DSP(TMS320LF2406) with A/D conversion data of the output current and voltage of each module. The developed converter is installed in PCU(Power Conditioning Unit) for HSG(High Speed Generator) in a vehicle and health monitoring system is implemented for vehicle operation test. Finally, performance of the developed converter is proved under practical operation of HSG.

• The Transactions of the Korean Institute of Power Electronics
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• v.14 no.6
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• pp.496-503
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• 2009

In this paper, a new three-phase interleaved isolated high efficiency boost dc-dc converter with active clamp is proposed. The converter is capable of increased power transfer due to its three-phase power configuration, and it reduces the rms current per phase, thus reducing conduction losses. Further, interleaved operation of three-phase boost converter reduces overall ripple current, which is imposed into fuel cells and realizes smaller sized filter components, increasing effective operating frequency and leading to higher power density. Each output current of three-phase boost converter is combined by the three-phase transformer and flows in the continuous conduction mode by the proposed three-phase PWM strategy. An efficiency of above 96% is mainly achieved by reducing conduction losses and switching losses are reduced by the action of active clamp branches, as well. The proposed converter and three-phase PWM strategy are analyzed, simulated and implemented in hardware. Experimental results are obtained on a 500 W prototype unit, with all of the design verified and analyzed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.1
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• pp.91-96
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• 2008

In this paper, a monopulse fled for three mode $2{\times}2$ array feed horn antenna was designed. Gain of single feed was 8.25dB. Increasing property of gain and rectangular waveguide and reflection of free space is decreased because it has structure extending to electric plane at connected part from transformation to free space. When fled port1 and port2 is placed vertically and thickness of aperture hem is reduced, isolation is satisfied with property of lower -25dB. Also, at higher frequency, it is confirmed that isolation is improved. Combination of electric field occurs less influence because port1 and port3 is placed horizontally and distribution of electric field is connected to parallel. However, because of combination of electric field, it is more improved from 2dB to 6dB than isolation of port1 and port2. Direct combination occult less effect at port1 and port4 than effect of port2 and port3, it is lower -35dB.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.1
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• pp.39-44
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• 2003

As the portable electronic equipments are developed and popularized, the batteies are more important. To prolong life of the equipments, engineers demand to have batteries of high-power density and they are used to use Li-ion batteries popularly Li-ion batteries are better than conventional batteries, Ni-cd, about power density per volume and weight, but they have a fault that discharge voltage of them goes down. In order to maximize life of the Li-ion batterries, we have to use a converter which is suitable for the characteristic of Li-ion batteries. Therefore, capacitive idling SEPIC(Single Ended Primary Inductance Converter) that is derived from the SEPIC topology is proposed as a source of the Portable low-power applications. The converter has characteristics of buck-boost porformance. Besides, that makes it possible to increase the switching frequency by partial soft commutation of power switches through adding a diode and a switch. This paper is presented the characteristics, DC voltage conversion ratio, circuits of operation modes, of the converter and it is analized and implemented.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.7
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• pp.791-799
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• 2008

In this paper, the electromagnetic modeling and network analysis are proposed for design of GTEM cell operating from DC to 18 GHz. 3D electromagnetic numerical analysis models composed of the coaxial mode-converter for the feeder of GTEM cell, 5 m expanded rectangular coaxial transmission line, and the resistive termination load for current and field transmitted from the feeder are developed. Equivalent network model of feeder, transmission line, and termination load in the GTEM cell is also proposed, so the return loss of GTEM cell is calculated using S-parameters using the electromagnetic numerical analysis. To verify the proposed design method, the GTEM cell is designed, constructed and tested, with its size of $5{\times}2.5{\times}1.7\;m$ and operating frequency of $DC{\sim}18\;GHz$.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.71-79
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• 2013

This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.