• Journal of KIISE:Computer Systems and Theory
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• v.37 no.2
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• pp.90-102
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• 2010

Flash memory has been widely used as an important storage device for consumer electronics. For the flash memory-based storage systems, FTL (Flash Translation Layer) is used to handle the mapping between a logical page address and a physical page address. Especially, log buffer-based FTLs provide a good performance with small-sized mapping information. In designing the log buffer-based FTL, one important factor is to determine the mapping structure between data blocks and log blocks, called associativity. While previous works use static associativity fixed at the design time, we propose a new log block mapping scheme which adjusts associativity based on the run-time workload. Our proposed scheme improves the I/O performance about 5~16% compared to the static scheme by adjusting the associativity to provide the best performance.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.20-29
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• 2006

The Java language has been established as one of the most widely used language due to its object-oriented programming, safety and flexibility and the garbage collection of the virtual machine has relieved programmers of many difficulties related to the memory management. In the embedded environment, Java is also prevalent, the virtual machine and garbage collector that takes into account the embedded environment is required. In this paper we manage the heap memory area by dividing into young generation and old generation, and we propose a garbage collector in which appropriate techniques are applied to each generation to utilize the different characteristics of each generation. Also, we propose the write barrier technique and double filtering technique for efficient garbage recognition, and double check method for determining and reclaiming the garbage with cyclic structure. The proposed method satisfies the embedded environment's requirements of fast object allocation, real time property, recollection of all the garbage, elimination of fragmentations and high locality.

• The Transactions of the Korea Information Processing Society
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• v.6 no.4
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• pp.1098-1105
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• 1999

The caches in distributed shared memory systems enhance the performance by reducing memory access latency and communication overhead, but they must solve the cache coherence problem. This paper proposes a new directory protocol to solve the cache coherence problem and to improve the system performance in distributed shared memory systems. To maintain the cache coherence of shared data, processors within a limited distance reduce the communication overhead by using a bit-vector like the full directory scheme. Processors over a limited distance store pointers in a directory pool. Since the bit-vector and the directory pool remove the unnecessary cache invalidations, the proposed scheme reduces the communication traffic and improves the system performance. The dynamic limited directory scheme reduces the communication traffic up to 66 percents compared with the limited directory scheme and the number of directory access up to 27 percents compared with the dynamic pointer allocation scheme.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.9
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• pp.898-903
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• 2010

Popularity of smartphones such as Google Android phones and Apple iphones, is increasing the demand on more reliable high performance file system for flash memory. In this paper, we propose two techniques to improve the performance of YAFFS (Yet Another Flash File System), while enhancing the reliability of the system. Specifically, we first propose to manage metadata and user data separately on segregated blocks and indexing information piggy-back technique for reducing mount time and also enhancing performance. Second, we tailor the wear-leveling to the segregated metadata and user data blocks. Performance evaluation results based on real hardware system with 1GB NAND flash memory show that the YAFFS with our proposed techniques realized outperforms the original YAFFS by six times in terms of mount speed and five times in terms of benchmark performance, while reducing the average erase count of blocks by 14%.

• The KIPS Transactions:PartA
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• v.13A no.4 s.101
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• pp.295-304
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• 2006

Java has been established as one of the most widely-used languages owing to its support of object-oriented concepts, safety, and flexibility. Garbage collection in the Java virtual machine is a core component that relieves application programmers of difficulties related to memory management. In this paper, we propose a memory manager and a garbage collector that is implemented on a embedded java virtual machine. The memory manager divide a heap into various-sized cells and manages it as blocks of same-sized cells. So it is possible to allocate and free memory fast. We adopted the 3-color based Mark & Sweep garbage collector as our base algorithm and we propose 4-color based Mark & Sweep garbage collector for supporting multi-threaded program. The proposed garbage collector occurs memory fragmentation but we show through a experiment that the fragmentation ratio is almost fixed according as we create objects continuously.

• Proceedings of the Korean Information Science Society Conference
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• 2003.10b
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• pp.91-93
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• 2003

본 논문에서는 대용랑 스토리지를 공유하는 스토리지 클러스터 시스템을 위한 매핑 테이블 기반의 스냅샷 기법을 제안한다. 스냅샷 상태 비트를 이용한 디스크 기반의 스냅샷 기법을 개선한 스냅샷 상태 테이블을 메모리에 유지하는 스냅샷 기법을 제안한다. 스냅샷 상태 테이블은 최초 할당 비트(FAB:First Allocation Bit)와 스냅샷 상태 비트(SSB:Snapshot Stautus Bit)로 구성되고 기존 스냅샷 기법이 갖는 문제점들을 해결한다. 스냅샷 생성 시 대상 저장 장치에 대한 I/O의 중단없이 데이터의 일관성을 보장한다. 또한 쓰기 연산 수행 시 COW의 수행 여부 판단을 스냅샷 상태 테이블의 FAB와 SSB를 이용하여 매핑 블록에 대한 추가적인 I/O를 없앤다. 스냅샷 삭제 시 매핑 블록에 대한 접근 없이 COW 수행 여부 판단을 처리하여 성능을 향상시킨다.

• Journal of KIISE
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• v.44 no.9
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• pp.878-886
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• 2017

This paper discusses performance bottlenecks that may occur when executing high-performance computing MPI applications in the Intel's next generation many-core processor called Knights Landing(KNL), as well as effective resource allocation techniques to solve this problem. KNL is composed of a host processor to enable self-booting in addition to an existing accelerator consisting of a many-core processor, and it was released with a new type of on-package memory with improved bandwidth on top of existing DDR4 based memory. We empirically verified an improvement of the execution performance of multiple MPI applications and the overall system utilization ratio by studying a resource allocation method optimized for such new many-core processor architectures.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1625-1635
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• 1997

An extension of the weighted buddy system, called the extended-weighted buddy system, for dynamic memory allocation in an object-oriented computer is presented. The extended-weighted buddy system allows block sizes of $2^k,\;3*2^k,\;5*2^k,\;7*2^k$, whereas the original weighted buddy system allowed block sizes of $2^k\;and\;3*2^k$. This extension is achieved at only the cost of additional 3 bits per block for memory management unit. Simulation results are presented which compare our method with the weighted buddy system. These results indicate that, for uniform request distributions, our system has less internal memory fragmentation than the weighted buddy system(approximately 60%). And, for exponential request distributions, it has less internal memory fragmentation than the weighted buddy method (approximately 50%). The external fragmentation is greater for this system than the weighted buddy system. But, our system has less total memory fragmentation for exponential request distributions, and two systems take a similar total memory fragmentation for uniform request distributions, so we can substitutes the extended-weighted buddy system for weighted buddy system.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.819-833
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• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• Journal of the Korea Society of Computer and Information
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• v.19 no.4
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• pp.17-24
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• 2014

Detecting data races is important for debugging shared-memory programs with nested parallelism, because races result in unintended non-deterministic executions of the program. It is especially important to detect the first occurred data races for effective debugging, because the removal of such races may make other affected races disappear or appear. Previous dynamic detection tools for first race detecting can not guarantee that detected races are unaffected races. Also, the tools does not consider the nesting levels or need support of other techniques. This paper suggests a post-mortem tool which collects candidate accesses during program execution and then detects the first races to occur on the program after execution. This technique is efficient, because it guarantees that first races reported by analyzing a nesting level are the races that occur first at the level, and does not require more analyses to the higher nesting levels than the current level.