• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.38-45
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• 2014

This paper proposes a characterization method based on the reference memory to characterize memory compiler quickly and accurately. In order to maintain the accuracy of the memory complier and to minimize characterization time, the proposed method models the trends of the generated memories by selecting the reference memories after analyzing the timing trends of the memory compiler. To validate the proposed method, we characterized the 110nm memory compiler derived from 130nm memroy compiler. The average error rate of the characteristics of the memories generated by the proposed method and SPICE simulation is lower than ${\pm}0.1%$. Furthermore, we designed memory BIST test chips at 110nm and 180nm processes and the results of the function test show that the yield is 98.8% and 98.3%, respectively. Therefore, the proposed method is useful to characterize the memory compiler.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3049-3054
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• 2000

In this paper, the effects of the hardware components and runtime environments on the overall performance of a distributed shared memory system are analyzed through simulation. In simulation, the system is modeled using PARSE[1.2] closely to the real runtime environment and the 2D FFT is virtually executed on it. The results of simulation show that the minor hardware components such as bus interfaces and local bus of a processor, which are usuallyignored or neglected when analyzing performance. have significant impacts on the overall system performance. Performance variations caused from runtime environments such as loop overhead and code optimuzatio are also analyzed quantitatively.

• KIISE Transactions on Computing Practices
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• v.23 no.3
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• pp.165-170
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• 2017

Many studies have utilized GPGPU (General-Purpose Graphic Processing Unit) and its high computing power to compute complex tasks. The characteristics of GPGPU programs necessitate the operations of memory copy between the host and device. A high latency period can affect the performance of the program. Thus, it is required to significantly improve the performance of GPGPU programs by optimizations. By executing multiple GPGPU programs simultaneously, the latency hiding effect of memory copy is achieved by overlapping the memory copy and computing operations in GPGPU. This paper presents the results of analyzing the latency hiding effect for memory copy operations. Furthermore, we propose a performance anticipation model and an algorithm for the limitations of using pinned memory, and show that the use of the proposed algorithm results in a 41% performance increase.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.994-997
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• 2003

행렬 연산은 계산 과학을 사용하는 공학 물리, 화학, 생명 과학, 경제학 등에서 다양하게 사용되고 있으며 이 행렬은 크기가 크고 대부분의 원소가 0 값을 갖는 희소 행렬일 경우가 많다. 본 논문에서는 희소 행렬의 연산 중, 회로 설계 시 최적화 과정에 사용되는 연산에서 문제가 되는 희소 행렬 A 와 블록 대각 행렬 H에 대하여 AH$A^{T}$ 의 연산을 효율적으로 행하는 방법들을 검토하고 메모리 접근 횟수를 모델링하여 수행 속도와 메모리 사용량 면에서 비교한다.

• Proceedings of the Korean Information Science Society Conference
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• 2002.10d
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• pp.61-63
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• 2002

복잡한 하드웨어 및 소프트웨어를 설계함에 있어 그 안정성에 대한 보장이 매우 중요하다. 이를 위해 정형 검증이나 테스팅과 같은 많은 기법을 활용하고 있다. 그러나 안정성 검증을 위해 시스템을 모델링하고 데스트 케이스를 만드는 과정에서 상태 폭발에 따른 메모리의 한계에 부딪히게 된다. 본 논문에서는 이러한 문제를 해결하고, 메모리를 효율적으로 이용할 수 있는 탐색방법을 이용한 데스트 케이스 생성 알고리즘을 제안한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.189-192
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• 2005

In this paper, we present a Petri Net (PN) model for reliability analysis of a shared database system. The system consists of components; a database, two processors, two memory and a bus. The database should be operational and at least one of the component should be also operational. Otherwise system will be down. Each component can be failed and repaired individually. Stochastic Reward Net (SRN) Model for reliability analysis is developed. SRN is potential to define various reward function and can be easily used to obtain performance measures. The modeling techniques using variable cardinality, enabling function, timed transition priority in SRN are shown.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05a
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• pp.92-97
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• 2002

자성체의 물성적인 성질에 바탕을 둔 Preisach 모델링은 히스테리시스 현상을 수치모사 하기 위한 방법으로 뛰어난 결과를 보여왔다. 하지만 Preisach 모델링은 그 계산과정에서 수렴의 어려움이 존재해 결과 값을 계산하지 못하는 경우가 발생하는 문제를 발생시켜왔었다. 본 논문에서는 Preisach 모델링을 프로그램하는데 있어서 기존에 발생했던 수렴의 문제점과 그 문제점을 해결하기 위한 보다 낳은 프로그램 기법들을 제시하였다. 이 방법은 기존 모델링 기법과 유사한 메모리를 사용하면서 수렴에 있어 향상된 결과를 얻을 수 있었다. 또한 Preisach 모델러를 개발하는 과정에 발생하는 Tracing 모델들을 도식화하여 Preisach 모델링에 대한 이해를 돕고자 하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.1-9
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• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.11
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• pp.1041-1049
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• 2012

The transactional memory was proposed to solve the problems of the conventional lock-based synchronization methods in the shared memory multiprocessor system. Various implementation methods for putting the high performance transactional memory to practical use have been continuously studied. However, these studies focus only on the commercialization and performance enhancement of the transactional memory. Besides, there have been few studies to analyze the system overhead of the transactional memory according to the conflict management policy. Thus this paper classifies hardware transactional memory, which is one kind of transactional memories, into four types according to the conflict management policy, and then compares and analyzes their performance and system bus traffic through their modeling and simulation. In addition, the most effective conflict management policy for the hardware transactional memory is presented through these comparison and analysis.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.