• Journal of KIISE:Computer Systems and Theory
• /
• v.35 no.6
• /
• pp.293-303
• /
• 2008

As the computing environment moves to the wireless and handheld system, the power efficiency is getting more important. That is the case especially in the embedded hand-held system and the power consumed by the memory system takes the second largest portion in overall. To save energy consumed in the memory system we can utilize low power mode of SDRAM. In the case of RDRAM, nap mode consumes less than 5% of the power consumed in active or standby mode. However hardware controller itself can't use this facility efficiently unless the operating system cooperates. In this paper we focus on how to minimize the number of active units of SDRAM. The operating system allocates its physical pages so that only a few units of SDRAM need to be activated and the unnecessary SDRAM can be put into nap mode. This work can be considered as a generalized and system-wide version of PAVM(Power-Aware Virtual Memory) research. We take all the physical memory into account, especially buffer cache, which takes an half of total memory usage on average. Because of the portion of buffer cache and its importance, PAVM approach cannot be robust without taking the buffer cache into account. In this paper, we analyze the RAM usage and propose power-aware page allocation policy. Especially the pages mapped into the process' address space and the buffer cache pages are considered. The relationship and interactions of these two kinds of pages are analyzed and exploited for energy saving.

• Journal of the Korea Computer Graphics Society
• /
• v.7 no.2
• /
• pp.1-9
• /
• 2001

본 논문은 여러 장의 이미지로부터 삼차원 모델을 빠르게 복원하기 위한 다각형 기반 Space Carving 알고리즘을 제안한다. 본 논문에서 제안하는 알고리즘은 기존의 복셀 carving 연산에 다각형 carving 연산을 추가하여 기존 복셀 carving 기법의 단점인 렌더링 품질의 저하와 느린 렌더링 속도 문제를 보완하였다. 따라서 복원된 모델은 다각형 구조를 가지며, 이로부터 텍스쳐 매핑을 이용한 빠른 속도의 고품질 렌더링 기법이 가능해진다. 또한 다각형 carving 후잉여 데이터를 삭제함으로써 복원된 모델의 품질 저하없이 메모리를 줄이고, 더욱 빠른 렌더링을 가능하게 한다.

• Proceedings of the KIEE Conference
• /
• 1989.11a
• /
• pp.488-493
• /
• 1989

In this paper, the structure of CMAC address mapping is first revisited, and the address hashing function and the random mapping is discussed in the conventional CMAC implementation. Then the effective size of CMAC memory is derived from the modulus property of the CMAC address vector, and a new hashing function for the effective memory mapping is proposed for a CMAC implementation with feasible memory size and no troublesome random mapping. Finally, the performance of the conventional CMAC learning algorithm and that of the proposed new CMAC scheme arc compared via simulations.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 1998.05a
• /
• pp.233-237
• /
• 1998

다중의 연속 미디어 데이타를 출력 마감시간(playout deadline)전에 검색 및 전송하여 자연스럽게 처리하기 위한 가장 효율적인 처리방안은 메모리 버퍼를 이용하는 것이다. 본 논문에서는 다중 스트림의 데이타 전송 요구 및 해제시의 버퍼 상태를 파악하여 버퍼를 동적으로 할당하고 물리작인 버퍼를 윈도우 크기의 논리버퍼로 분할하여 동적으로 관리하는 매핑관리자를 설계하여 버퍼이용률을 높일 수 있는 방안을 제시하였다. 또한, 서로 다른 소비율로 발생된 여분의 버퍼 공간을 활용할 수 있는 지능적인 선반입 기법과 마감시간을 고려한 전송 스케줄링 기법을 통해 실시간에 동기식으로 다중 미디어 스트림을 전송할 수 있는 동적 버퍼 관리 기법을 제안하였다. 마지막으로, 버퍼의 이용율을 높이기 위해 입출력 주기에 따라 버퍼 공간을 여러 스트림들이 파이프라이닝 방식으로 버퍼를 공유하는 기법과 잔여 버퍼공간의 할당 여부를 결정하기 위한 수락제어 기법을 적용하였다.

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.9
• /
• pp.407-415
• /
• 2007

In parallel cluster computing systems, the efficiency of communication between computing nodes is one of important factors that decide overall system performance. Accordingly, many researchers have studied on high-performance inter-node communication. The recently launched multi-core processor, however. increases the importance of intra-node communication as well because the more the number of cores in a node, the more the number of parallel processes running in the same node. Though there have been studies on intra-node communications, these have limited considerations on the state-of-the-art systems. In this paper, we propose a Linux kernel module that minimizes the number of data copy by exploiting the memory mapping mechanism for high-performance intra-node communication. The proposed kernel module supports the Linux kernel version 2.6. The performance measurements over a multi-core system present that the proposed kernel module can achieve lower latency up to 62% and higher throughput up to 144% than an existing kernel module approach. In addition, the measurements reveal that the performance of intra-node communication can vary significantly based on whether the cores that run the communication processes are belong to the same processor package (i.e., sharing the L2 cache).

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.2
• /
• pp.57-64
• /
• 2007

This paper proposed the low power texture cache for mobile 3D graphics accelerators. It is very important to reduce the leakage power in the standby mode for mobile 3D graphics accelerators and the memory access latency of texture mapping in the active mode which needs a large memory bandwidth. The proposed structure reduces the leakage power using variable threshold values of power mode transitions according to the selected texture filtering algorithms of application programs, which has the run time gain for texture mapping. In the trace driven cache simulation the proposed structure shows the best 7% performance gain to the previous MSA cache according to the new performance metric considering both normalized leakage power and run time impact.

• The Journal of the Korea Contents Association
• /
• v.10 no.6
• /
• pp.72-79
• /
• 2010

In this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using $0.13-{\mu}m$ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor.

• The KIPS Transactions:PartA
• /
• v.13A no.2 s.99
• /
• pp.123-136
• /
• 2006

The prefetching technique is an effective way to reduce the latency caused memory access. However, excessively aggressive prefetch not only leads to cache pollution so as to cancel out the benefits of prefetch but also increase bus traffic leading to overall performance degradation. In this thesis, a prefetch filtering scheme is proposed which dynamically decides whether to commence prefetching by referring a filtering table to reduce the cache pollution due to unnecessary prefetches In this thesis, First, prefetch hashing table 1bitSC filtering scheme(PHT1bSC) has been shown to analyze the lock problem of the conventional scheme, this scheme such as conventional scheme used to be N:1 mapping, but it has the two state to 1bit value of each entries. A complete block address table filtering scheme(CBAT) has been introduced to be used as a reference for the comparative study. A prefetch block address lookup table scheme(PBALT) has been proposed as the main idea of this paper which exhibits the most exact filtering performance. This scheme has a length of the table the same as the PHT1bSC scheme, the contents of each entry have the fields the same as CBAT scheme recently, never referenced data block address has been 1:1 mapping a entry of the filter table. On commonly used prefetch schemes and general benchmarks and multimedia programs simulates change cache parameters. The PBALT scheme compared with no filtering has shown enhanced the greatest 22%, the cache miss ratio has been decreased by 7.9% by virtue of enhanced filtering accuracy compared with conventional PHT2bSC. The MADT of the proposed PBALT scheme has been decreased by 6.1% compared with conventional schemes to reduce the total execution time.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.41 no.6
• /
• pp.147-154
• /
• 2004

In this paper, Inverted Coordinates Image Space (ICIS) is proposed as a solution for the problem of the unbounded accumulator space in the automatic detection of the finite/infinite vanishing points in image space. Since the ICIS is based on the direct transformation from the image space, it does not lose any geometrical information from the original image and it does not require camera calibration as opposed to the Gaussian sphere based methods. Moreover, the proposed method can accurately detect both the finite and infinite vanishing points under a small fixed memory amount as opposed to the conventional image space based methods. Experiments are conducted on various real images in architectural environments to show the advantages of the proposed approach over conventional methods.

• Journal of KIISE:Databases
• /
• v.28 no.4
• /
• pp.723-731
• /
• 2001

As XML has become and emerging standard for information exchange on the World Wide Web it has gained attention in database communities of extract information from XML seen as a database model. Data in XML can be mapped to semistructured dta model based on edge-labeled graph and queries can be processed against it Here we propose new query optimization techniques using DTDs(Document Type Definitions) which have the schema information about XML data. Our techniques reduce traditional index techniques Also, as they preserve source database structure, they can process many kinds of complex queries. we implemented our techniques and provided preliminary performance results.