• Journal of KIISE
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• v.45 no.1
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• pp.9-14
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• 2018

Tar is a Linux command that combines several files into a single file. Combining multiple small files into large files increases the compression efficiency and data transfer speed. However, tar has a problem in that smaller target files, result in a lower performance. In this paper, we show that this performance degradation occurs when tar reads the data from the target files and propose qtar (quick tar) to solve this problem via flash-level remapping. When the size of an I/O request is less than 1 MB, the I/O performance decreases proportionally to the decrease in size of the I/O request. Since tar reads the data of files one by one, a smaller file size results in a lower performance. Therefore, the remapping technique is implemented in qtar to read data from the target files at the maximum I/O size regardless of the size of each file. Our evaluations show that the execution time with qtar is reduced by up to 3.4 times compared to that with tar.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.62-70
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• 2007

In this paper, we design a mobile camera processor to support the MIPI CSI-2 and DPHY specification. The lane management sub-layer of CIS2 handles multi-lane configuration. Thus conceptually, the transmitter and receiver have each independent buffer on multi lanes. In the proposed architecture, the independent buffers are merged into a single common buffer. The single buffer architecture can flexibly manage data on multi lanes though the number of supported lanes are mismatched in a camera processor transmitter and a host processor. For a key issue for the data synchronization problem, the synchronization start codes are added as the starting for image data. We design synchronization logic to synchronize the received clock and to generate the byte clock. We present the verification results under proposed test bench. And we show the waves of simulation and logic synthesis results of the designed processor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.313-315
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• 2010

In this paper, we describe research results of developing hardware rasterizer that is applicable to mobile 3D graphics system, designed in SIMD architecture and verified in FPGA. Tile-based scan conversion unit is designed like SIMD architecture running four tiles simultaneously and each tile traverses pixels hierarchical in 3-level so that visiting counts is minimized. As experimental results, $8{\times}8$ is the most efficient size of tile and the last step of tile traversing is performed on $2{\times}2$ sized subtile. The rasterizer supports flat shading and gouraud shading and texture mapper supports affine mapping and perspective corrected mapping. Also, texture mapper supports point sampling mode and bilinear interpolating sampling mode and two types of wrapping modes and various blending modes. The rasterzer operates as 120Mhz on xilinx vertex4 $l{\times}100$ device. To easy verification, texture memory and frame buffer are generated as block rom and block ram.

• The KIPS Transactions:PartA
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• v.14A no.3 s.107
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• pp.151-158
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• 2007

Quadtree, which is a hierarchical data structure, is a very important data structure to represent images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The computation of block location is one of important geometry operations in image processing, which extracts a component completely including a given block. In this paper, we present a constant time algorithm to compute the block location of images represented by quadtrees, using three-dimensional $n\times n\times n$ processors on RMESH(Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to deal with the locational codes of quardtree on the hierarchical structure of $n\times n\times n$ RMESH.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.207-214
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• 2003

Quadtree, which is a hierarchical data structure, is a very important data structure to represent binary images. The linear quadtree representation as a way to store a quadtree is efficient to save space compared with other representations. Therefore, it has been widely studied to develop efficient algorithms to execute operations related with quadtrees. The linear translation is one of important operations in image processing, which moves the image by a given distance. In this paper, we present an algorithm to perform the linear translation of binary images represented by quadtrees, using three-dimensional $n{\times}n{\times}n$ processors on RMESH (Reconfigurable MESH). This algorithm has constant-time complexity by using efficient basic operations to route the locational codes of quardtree on the hierarchical structure of n${\times}$n${\times}$n RMESH.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2247-2258
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• 1997

Quadtree, which is hierarchical data structure, is a very important data structure to represent binary images. Since a linear quadtree representation as is a way to store a quadtree is efficient to save space compared with other representations. It is, however, complicated and takes a large amount of time to build the linear quadtree. In this paper, we present O(1) time a linear quadtree building algorithm for a $n{\times}n$ binary image using three-dimensional $n{\times}n{\times}n$ processors on RMESH structure. Our algorithm, by use of O(1) time collapsing algorithm and reported O(1) time sorting algorithm, is simpler and easier to understand than resently presented algorithm on PARBUS structure.

• Convergence Security Journal
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• v.12 no.1
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• pp.3-8
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• 2012

MANET composed wireless nodes without fixed infrastructure provides high flexibility, but it has weak disadvantage to various attack. It has big weakness to DDoS attack because every node perform packet forwarding especially. In this paper, packet transmission information control technique is proposed to reduce damage of DDoS attack in MANET and search location of attacker when DDoS attacks occur. Hierarchical structure using gateway node is adopted for protect a target of attack in this study. Gateway node in cluster is included like destination nodes surely when source nodes route path to destination nodes and it protects destination nodes. We confirmed efficiency by comparing proposed method in this study with CUSUM and measured the quantity consumed memory of cluster head to evaluate efficiency of information control using to location tracing.

• Journal of the Korea Society of Computer and Information
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• v.25 no.3
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• pp.51-55
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• 2020

In this paper, an improved FAM is proposed by adopting similarity learning in the existing FAM (Fuzzy Associative Memory) used in image restoration. Image restoration refers to the recovery of the latent clean image from its noise-corrupted version. In serious application like face recognition, this process should be noise-tolerant, robust, fast, and scalable. The existing FAM is a simple single layered neural network that can be applied to this domain with its robust fuzzy control but has low capacity problem in real world applications. That similarity measure is implied to the connection strength of the FAM structure to minimize the root mean square error between the recovered and the original image. The efficacy of the proposed algorithm is verified with significant low error magnitude from random noise in our experiment.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.5
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• pp.656-662
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• 2018

Pattern matching algorithm is widely used in many application fields such as bio-informatics, intrusion detection, etc. Among many string matching algorithms, KMP (Knuth-Morris-Pratt) algorithm is commonly used because of its fast execution time when using large texts. However, the processing speed of KMP algorithm is also limited when the text size increases significantly. In this paper, we propose a high throughput parallel KMP algorithm considering CPU-GPU memory hierarchy based on OpenCL in GPGPU (General Purpose computing on Graphic Processing Unit). We focus on the optimization for the allocation of work-times and work-groups, the local memory copy of the pattern data and the failure table, and the overlapping of the data transfer with the string matching operations. The experimental results show that the execution time of the optimized parallel KMP algorithm is about 3.6 times faster than that of the non-optimized parallel KMP algorithm.