• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.5
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• pp.389-394
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• 2004

In this paper, according to characteristics of flash memory, a memory recycling method is proposed in order to decrease the necessary cost preventing performance degradation at the same time, In order to optimize the demanding costs, the new approach partitions the search space of flash memory segments into K segment groups, A method for memory space allocation, in addition, is proposed in order to satisfy the goal of even wearing over the total memory space, The optimized configuration of the proposed method is achieved through experiments, The fact that the newly proposed methods outperform the existing approaches regarding cost and performance is evaluated by simulations, Furthermore the experimental results demonstrate that the memory allocation method affects even wearing in great deal.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.1
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• pp.105-111
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• 2013

We have developed an analog associative memory implemented with an analog array which has linear writing and erasing characteristics. The associative memory adopts a winner-take-all strategy. The operation for reading in the memory is executed with an absolute differencing circuit and a winner-take-all (WTA) circuit suitable for a nearest-match function of a content-addressable memory. We also present a system architecture that enables highly-paralleled fast writing and quick readout as well as high integration density. A multiple memory cell configuration is also presented for achieving higher integration density, quick readout, and fast writing. The system technology presented here is ideal for a real time recognition system. We simulate the function of the mechanism by menas of Hspice with $1.2{\mu}$ double poly CMOS parameters of MOSIS fabrication process.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1529-1534
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• 2013

Since a NAND-flash memory is able to store mass data in a small sized chip and consumes low power, it is exploited on various hand-held devices, such as a smart phone and a sensor node, etc. To process efficiently mass data stored in the flash memory, it is required to use an index. However, since the write operation of the flash memory is slower than the read operation and an overwrite operation is not supported, the usage of existing index schemes degrades the performance of the index. In this paper, we survey the previous researches of index schemes for the flash memory and classify the researches by the methods to solve problems. We also present the performance factor to be considered when we design the index scheme on the flash memory.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.3
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• pp.477-486
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• 2022

This study aims to present a method using event sourcing patterns and blockchain as a way to cope with vulnerabilities in memory manipulation at the client level. To verify the plan, the method of running the memory operation application was analyzed, and the performance was compared and analyzed when the memory operation prevention plan was applied by fabricating a test application. As a result of the analysis, the usage of memory increased compared to the method of XOR operation by storing major data in one memory, but it was possible to prevent the operation of the memory operation program without significantly affecting the performance of the game.

• Journal of KIISE:Databases
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• v.37 no.6
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• pp.292-299
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• 2010

Recently, as flash memory is used as digital storage devices, necessity for digital forensics is growing in a flash memory area for digital evidence analysis. For this purpose, it is important to recover crashed files stored on flash memory efficiently. However, it is inefficient to apply the hard disk based file recovery techniques to flash memory, since hard disk and flash memory have different characteristics, especially flash memory being unable to in-place update. In this paper, we propose a flash-aware file recovery technique for digital forensics. First, we propose an efficient search technique to find all crashed files. This uses meta-data maintained by FTL(Flash Translation Layer) which is responsible for write operation in flash memory. Second, we advise an efficient recovery technique to recover a crashed file which uses data location information of the mapping table in FTL. Through diverse experiments, we show that our file recovery technique outperforms the hard disk based technique.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.600-603
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• 2008

In this paper, a new circuit design named memory-in-pixel for low power consumption of the liquid crystal display (LCD) is presented. Since each pixel has a memory, it is able to express 8 color grades using the data saved in the memory without the operation of the gate and source driver ICs so that it can reduce the power consumption of the LCD panel. A memory circuit consists of modified S-R flip-flop (NAND-type) implemented in the pixel, which can supply AC bias for operating the liquid crystal (LC) with the interlocking clocks (CLK_A and CLK_B). This circuit is more complex than the inverter-type memory circuit, but it has lower power consumption of approximately 50% than the circuit. We have investigated the power consumption both NAND and inverter-type memory circuit using a Smart SPICE for the resolution of $96{\times}128$. The estimated power consumption of the inverter-type memory was about 0.037mW. On the other hand, the NAND-type memory showed power consumption of about 0.007mW.

• Journal of KIISE
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• v.42 no.2
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• pp.183-189
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• 2015

Recently, computer systems have encountered difficulties in making further progress due to the technical limitations of DRAM based main memory technologies. This has motivated the development of next generation memory technologies that have high density and non-volatility. However, these new memory technologies also have their own intrinsic limitations, making it difficult for them to currently be used as main memory. In order to overcome these problems, we propose a hybrid main memory system, namely HyMN, which utilizes the merits of next generation memory technologies by combining two types of memory: Write-Affable RAM(WAM) and Read-Affable RAM(ReAM). In so doing, we analyze the appropriate WAM size for HyMN, at which we can avoid the performance degradation. Further, we show that the execution time performance of HyMN, which provides an additional benefit of durability against unexpected blackouts, is almost comparable to legacy DRAM systems under normal operations.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.57-62
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• 2022

Recently, fast storage media such as phage-change memory (PCM) emerge, and memory management policies for slow disk storage need to be revisited. In this paper, we propose a new page replacement policy that makes use of PCM as a swap device of virtual memory systems. The proposed policy aims at reducing write traffic to the swap device as well as reducing the number of page faults pursued by traditional page replacement policies. This is because a write operation in PCM is slow and PCM has limited write endurances. Specifically, the proposed policy focuses on the reduction of page faults when the memory load of the system is high, but it aims at reducing write traffic to storage when free memory space is sufficient. Simulation experiments with various memory reference traces show that the proposed policy reduces write traffic to PCM without performance degradations.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.7
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• pp.71-79
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• 2012

As advances in computer technology, dissemination of smartphones and tablet PCs has increased and digital media has become easily accessible. The performance of computer hardware is improved and the form of hardware is changed, but basically the change in mechanism was not occurred. Typically, the data used in the program is resident in memory during the operation because of the operating system efficiency. So, these data in memory is accessible through the memory dumps or real-time memory analysis. The user's personal information or confidential data may be leaked by exploiting data; thus, the countermeasures should be provided. In this paper, we proposed the method that minimizes user's data leakage through finding the physical memory address of the process using virtual memory address, and initializing memory data of the process.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.4
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• pp.919-928
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• 2018

Out-Of-Bounds (OOB) is one of the most powerful vulnerabilities in heap memory. The OOB vulnerability allows an attacker to exploit unauthorized access to confidential information by tricking the length of the array and reading or writing memory of that length. In this paper, we propose a method to automatically detect OOB vulnerabilities in heap memory using dynamic symbol execution and shadow memory table. First, a shadow memory table is constructed by hooking heap memory allocation and release function. Then, when a memory access occurs, it is judged whether OOB can occur by referencing the shadow memory, and a test case for causing a crash is automatically generated if there is a possibility of occurrence. Using the proposed method, if a weak block search is successful, it is possible to generate a test case that induces an OOB. In addition, unlike traditional dynamic symbol execution, exploitation of vulnerabilities is possible without setting clear target points.