• KIPS Transactions on Computer and Communication Systems
• /
• v.4 no.5
• /
• pp.153-160
• /
• 2015

The effectiveness of multicores depends on how well a scheduler can assign tasks onto the cores efficiently. In a heterogeneous multicore platform, the execution time of an application depends on which core it executes on. That is to say, the effectiveness of task assignment is one of the important components for a multicore systems' performance. This work proposes a load scheduling technique that analyzes execution time of each task by profiling. The profiling result provides a basic information to predict which task-to-core mapping is likely to provide the best performance. By using such information, the proposed technique is about 26% performance gain.

• Proceedings of the Korean Information Science Society Conference
• /
• 2008.06b
• /
• pp.405-410
• /
• 2008

성능 / 에너지를 강조하는 현재의 멀티코어 추세에서 임베디드 시스템에 사용되는 대부분의 프로세서들은 단일 프로세서와 메모리를 버스 형태로 연결하여 구현하였다. 하지만 칩 내부의 프로세서 코어 수가 증가 하게 되면, 기존 버스 형태의 구조는 제한된 대역폭으로 인하여 확장성이 제약된다. 본 논문에서는 멀티코어 프로세서에서 사용 가능한 기존 연결 망 구조들을 분석하고, 기존 계층적 링 구조에서의 지연 시간 문제를 극복하여 성능을 개선할 수 있는 새로운 이중 광역 계층 링 구조를 제안한다.

• Journal of Korea Multimedia Society
• /
• v.14 no.11
• /
• pp.1478-1490
• /
• 2011

Recently, multi-core processors have been drawing significant interest from the embedded systems research and industry communities due mainly to their potential for achieving high performance and fault-tolerance at low cost in such products as automobiles and cell phones. To process multimedia data, a scheduling algorithm is required to meet timing constraints of periodic tasks in the system. Though Pfair scheduling algorithm can meet all the timing constraints while achieving 100% utilization on multi-core based system theoretically, however, the algorithm incurs high scheduling overheads including frequent core migrations and system-wide synchronizations. To mitigate the problems, we propose a real-time scheduling algorithm for multi-core based system so that system-wide scheduling is performed only when it is absolutely necessary. Otherwise the proposed algorithm performs scheduling within each core independently. The experimental results by extensive simulations show that the proposed algorithm dramatically reduces the scheduling overheads up to as negligible one when the utilization is under 80%.

• Proceedings of the Korean Information Science Society Conference
• /
• 2012.06a
• /
• pp.245-247
• /
• 2012

최근 멀티코어 프로세서의 활용이 대중화되고 있다. 멀티코어 시스템에서는 소프트웨어가 동시에 여러 코어를 사용하여 동작을 수행 할 때 성능 향상 효과를 얻을 수 있다. 즉, 하나의 소프트웨어가 여러 코어를 동시에 사용할 수 있는 멀티스레드 프로그래밍 기법을 사용할 때 성능을 높일 수 있다. 이러한 환경에서 효율적인 메모리 할당은 데스크톱, 서버 및 과학 등과 같은 응용에 매우 중요하다. 하지만, 동적으로 메모리를 할당하는 것은 메모리 할당 연산과 반환 연산 및 어떤 스레드가 다른 스레드의 힙 영역에 접근하는 것을 처리하기 위한 동기화 문제로 인한 오버헤드가 발생하여 성능에 영향을 끼치는 문제가 발생하게 된다. 따라서 이와 같은 환경에서 실제로 성능에 어느 정도 영향을 끼칠 것인가를 측정할 수 있는 도구가 필요하다. 이에 멀티코어 환경에서 멀티스레드 기법을 사용하여 메모리 할당 연산이 성능에 어떠한 영향을 끼치는지를 측정 및 평가할 수 있는 시뮬레이터인 MAES(Memory Allocation Evaluation Simulator)를 설계하고 구현한다.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.12
• /
• pp.968-972
• /
• 2009

The multi-core processors are being widely exploited by many high-end systems. With significant advances in processor architecture, the network band-width required on the high-end systems is increasing drastically. It is therefore highly desirable to manage multiple cores efficiently to achieve high network band-width with minimum resource requirements. Modern operating systems, however, still have significant design and optimization space to leverage the network performance over multi-core systems. In this paper, we suggest a novel networking process scheduling scheme, which decides the best processor affinity of networking processes based on the processor cache layout, communication intensiveness, and processor loads. The experimental results show that the scheduling scheme implemented in the Linux kernel can improve the network bandwidth and the effectiveness of processor utilization by 20% and 59%, respectively.

• The KIPS Transactions:PartC
• /
• v.10C no.3
• /
• pp.377-386
• /
• 2003

This study suggested a technique to maintain an efficient core-based multicast tree using weighted clustering factors in mobile Ad-hoc networks. The biggest problem with the core-based multicast tree routing is to decide the position of core node. The distance of data transmission varies depending on the position of core node. The overhead's effect on the entire network is great according to the recomposition of the multicast tree due to the movement of core node, clustering is used. A core node from cluster head nodes on the multicast tree within core area whose weighted factor is the least is chosen as the head core node. Way that compose multicast tree by weighted clustering factors thus and propose keeping could know that transmission distance and control overhead according to position andmobility of core node improve than existent multicast way, and when select core node, mobility is less, and is near in center of network multicast tree could verification by simulation stabilizing that transmission distance is short.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2003.11b
• /
• pp.999-1002
• /
• 2003

최근 인터넷 환경의 향상에 따라 네트워크는 멀티미디어 서비스 범위 확대와 효율적인 네트워크 자원 사용을 위해서 멀티캐스팅 기술을 지원하는 것이 바람직하다. 멀티캐스트 라우팅 프로토콜은 소스 기반 트리와 코어 기반 트리 방식으로 분류할 수 있다. 소스 기반 트리 방식은 멀티캐스트 그룹에서 소스 당 하나의 트리를 형성하게 되는 반면에 코어 기반 트리 방식은 그룹의 모든 노드가 하나의 트리를 공유한다. 이런 코어 기반 트리 방식에서는 코어 혹은 센터의 위치에 따라 멀티캐스트 라우팅 트리의 모양이 영향을 받으며 그에 따라 라우팅의 성능에 중대한 영향을 주게 된다. 본 논문에서는 공유 트리를 형성하는 라우팅 아키텍쳐에서 코어의 위치를 결정하기 위한 기존 방법들을 분석하며 성능 향상을 고려한 방안을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.11a
• /
• pp.66-68
• /
• 2011

낮은 오버헤드를 갖는 실시간 스케줄링 알고리즘은 멀티코어 프로세서가 임베디드 시스템에서 사용되기 위한 가장 중요한 요소 중의 하나이다. 멀티코어 환경에서 스케줄링 오버헤드는 주로 메모리 성능을 저해시키는 코어간 태스크 이동에 의해 발생한다. 본 논문에서는 시스템 이용률 면에서 최적으로 알려진 Pfair 스케줄링 알고리즘을 스케줄링 시에 태스크의 CPU 코어 할당 방식에 대해 스케줄링 오버헤드를 측정하였다. 실험 결과 동일 코어 기반 태스크 할당 방식을 도입함으로 인해서 태스크 이동 횟수를 크게 줄일 수 있음을 보여주었다.

• Journal of the Korea Society of Computer and Information
• /
• v.17 no.6
• /
• pp.1-11
• /
• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• The KIPS Transactions:PartA
• /
• v.16A no.2
• /
• pp.113-124
• /
• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.