• 한국지구물리탐사학회:학술대회논문집
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• 2009.10a
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• pp.75-80
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• 2009

Despite its flexibility to complex geometry, three-dimensional (3D) electromagnetic(EM) modeling schemes using finite element method (FEM) have been faced to practical limitation due to the resulting large system of equations to be solved. An efficient 3D FEM modeling scheme has been developed, which can adopt either direct or iterative solver depending on the problems. The direct solver PARDISO can reduce the computing time remarkably by incorporating parallel computing on multi-core processor systems, which is appropriate for single frequency multi-source configurations. When limited memory, the iterative solver BiCGSTAB(1) can provide fast and stable convergence. Efficient 3D simulations can be performed by choosing an optimum solver depending on the computing environment and the problems to be solved. This modeling includes various types of controlled-sources and can be exploited as an efficient engine for 3D inversion.

• Journal of Korea Multimedia Society
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• v.7 no.11
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• pp.1630-1638
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• 2004

The ultimate purpose of game production is to make a game which satisfy game players and to sell maximum of products. In this paper, we suggest an assessment system model which can evaluate game satisfaction degree quantitatively, for preparing foundations that can make games which the suppliers and demanders of game business want. For it, we computed weight of constituent factors for game with AHP method based on survey, and quantified degree of satisfaction for genre of games to score. Also we analyzed affective factors for game satisfaction by SEM using LISREL software. In result, the greatest affective factor for game satisfaction is fun. For making the game with high degree of satisfaction, we propose that constructive investment and enough technology for fun are needed.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.93-99
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• 2017

In this research the TOF (time of flight) of ultrasonic signal is measured using Xilinx's Zynq SoC (system on chip). The TOF is calculated from the difference between periods during which RF (radio frequency) and ultrasonic signals come across a distance, and then travelling distance is obtained by multiplying the TOF by the ultrasonic speed in the air. For this purpose, a ultrasonic pulse is generated from a Zynq's internal ADC, a FIR (finite impulse response) filter, and a Kalman filter. And a RF reference pulse is generated from a RF interface. Based on baremetal multiprocessing, the Kalman filter and the RF interface are c-programmed on Zynq's dual processor cores, with other components fabricated on Zynq's FPGA. With this HW/SW co-design, both lower resource utilization and much smaller designing period were obtained than the HW design. As a design tool, Vivado IDE(integrated design environment) is used to design the whole signal processing system in hierarchical block diagrams.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.4
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• pp.231-243
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• 2009

Many DSP systems are streaming applications in which streams of data constantly flow through a set of filters. Dataflow programming paradigm is one of effective methods for representing these streaming applications. Dataflow programming model explicitly exposes parallelisms within an application, which helps compiling of the application onto a multicore platform. We propose SPEX(Signal Processing Extension), a language extension to a standard imperative language based on the parameterized dataflow model. Parameterized dataflow model is a kind of dataflow model that can express a modest fashion of dynamism contrary to the synchronous dataflow that can represent only static dataflow. SPEX facilitates characterizing an application written in conventional imperative languages such C/C++ as a streaming application. SPEX is comprised of a few keywords augmented to the conventional C++ syntax for representing dataflow paradigm. SPEX also restricts the syntax and semantics of C++ in order to fit the program within a certain streaming programming category. In this paper, we focus on the capability of SPEX in representing streaming computations within filters and streaming communications among filters.

• Proceedings of the Korea Water Resources Association Conference
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• 2016.05a
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• pp.72-72
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• 2016

최근 발생하고 있는 기후변화로 인하여 하천 및 저수지의 수질문제가 커지고 있다. 특히 여름철 부영양화로 인해 발생하는 녹조현상은 사회적인 문제로 과학적인 수질사고에 대한 예측과 관리가 필요한 실정이다. 수질예보는 정기적으로 하천 및 저수지의 수질을 예측하여 사용자에게 제공하는 분석기법으로 수질현황을 파악하고 수질을 관리하고 의사결정을 하는데 도움을 줄 수 있다. 수질예보에 사용되는 모형은 유역모형, 하천모형, 저수지모형이 있으며, 이중 하천 및 저수지에 주로 적용되고 있는 3차원 수리수질모형의 경우 격자의 개수가 많아 모의시간이 길어지게 되고 이로 인해 일일 수질 예보가 어렵게 된다. 3차원 수리수질모형의 모의속도를 개선하는 방법에는 하드웨어의 성능을 높이는 방법과 병렬화를 이용한 소프트웨어적인 방법이 있다. 이중 하드웨어의 성능을 높이는 방법은 컴퓨터의 사양을 높이는 방법으로 높은 비용이 소요된다. 하지만 병렬화 방법은 컴퓨팅 기술의 발전으로 멀티코어가 대중화가 된 최근에 코드의 적용만으로 모의속도를 향상시킬 수 있다. 본 연구에서 사용된 모형은 서호주대학에서 개발한 3차원 수리 수질모형인 ELCOM-CAEDYM 모형으로 적용된 병렬화 기법은 OpenMP(Open Multi-Processing)방법이다. 기존 직렬 컴퓨팅 방식으로 구성되어 한번에 한 개의 명령어 밖에 처리할 수 없었던 작업방법을 동시에 여러 개의 처리요소를 이용하여 명령을 실행할 수 있게 하는 방식이다. 하지만 CPU의 개수는 제한되어 있으며, Amdahl's law에 따르면 OpenMP방식의 병렬화시 속도개선효과는 95% 병렬화 프로그램에서 최대 CPU 개수의 제한이 없다면 20배 까지 속도향상이 가능하다고 하였다. 본 연구에서는 3차원 수리 수질예측 모형인 ELCOM-CAEDYM에 적용된 병렬화 기법을 적용하는데 있어 최적 CPU사용 개수를 파악 하고자 하였으며, 이를 통해 수질예보시스템을 운영하는데 가장 효율적인 방법을 찾아 적용하고자 하고자 한다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.5
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• pp.11-18
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• 2021

The small radio frequency tracking radar is a tracking system with a radio frequency sensor that identifies a target through all-weather radio frequency signal processing for a target and searches, detects and tracks the target for the major target. In this paper, we describe the development of a board equipped with TMS320C6678 and XILINX FPGA (Field Programmable Gate Array), a high-speed multi-core DSP that acquires target information through all-weather radio frequency and identifies a target through real-time signal processing. We propose DSP-FPGA combination architecture for DSP and FPGA selection and signal processing, and also explain the design of SRIO for high-speed data transmission.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.57-64
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• 2019

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.2
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• pp.227-242
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• 2022

This paper presents a Cache-Coherency Interconnect(CCI)-based Android pattern screen lock(PSL) attack on modern ARM processors. CCI has been introduced to maintain the cache coherency between the big core cluster and the little core cluster. That is, CCI is the central interconnect inside SoC that maintains cache coherency and shares data. In this paper, we reveal that CCI can be a side channel in security, that an adversary can observe security-sensitive operations. We design and implement a technique to compromise Android PSL within only a few attempts using the information of CCI in user-level applications on Android Nougat. Further, we analyzed the relationship between the pattern complexity and security. Our evaluation results show that complex and simple patterns would have similar security strengths against the proposed technique.