• Journal of the Korea Institute of Information Security & Cryptology
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• v.32 no.2
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• pp.227-242
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• 2022

This paper presents a Cache-Coherency Interconnect(CCI)-based Android pattern screen lock(PSL) attack on modern ARM processors. CCI has been introduced to maintain the cache coherency between the big core cluster and the little core cluster. That is, CCI is the central interconnect inside SoC that maintains cache coherency and shares data. In this paper, we reveal that CCI can be a side channel in security, that an adversary can observe security-sensitive operations. We design and implement a technique to compromise Android PSL within only a few attempts using the information of CCI in user-level applications on Android Nougat. Further, we analyzed the relationship between the pattern complexity and security. Our evaluation results show that complex and simple patterns would have similar security strengths against the proposed technique.

• Korean Journal of Optics and Photonics
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• v.24 no.4
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• pp.184-188
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• 2013

Two types of polymer-based optical splitters with $200{\mu}m$ large core are presented for optical multimode networks, such as smart home networks, intelligent automotive networks, etc. Optical splitters that have 1:1 symmetric and 9:1 asymmetric structure were fabricated by a ultra violet(UV)-imprint technology using a deep etched Si(silicon) master by the Bosch process. In this paper, we successfully fabricated the symmetric and asymmetric optical splitters with suitable optical network applications.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.35 no.3
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• pp.187-194
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• 2017

The present study introduces a method to parallelize k-means clustering algorithm for fast unsupervised classification of large satellite imagery. Known as a representative algorithm for unsupervised classification, k-means clustering is usually applied to a preprocessing step before supervised classification, but can show the evident advantages of parallel processing due to its high computational intensity and less human intervention. Parallel processing codes are developed by using multi-threading based on OpenMP. In experiments, a PC of 8 multi-core integrated CPU is involved. A 7 band and 30m resolution image from LANDSAT 8 OLI and a 8 band and 10m resolution image from Sentinel-2A are tested. Parallel processing has shown 6 time faster speed than sequential processing when using 10 classes. To check the consistency of parallel and sequential processing, centers, numbers of classified pixels of classes, classified images are mutually compared, resulting in the same results. The present study is meaningful because it has proved that performance of large satellite processing can be significantly improved by using parallel processing. And it is also revealed that it easy to implement parallel processing by using multi-threading based on OpenMP but it should be carefully designed to control the occurrence of false sharing.

• KNOM Review
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• v.23 no.2
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• pp.29-41
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• 2020

Networks are growing faster than ever before causing a multi-domain complexity. The diversity, variety and dynamic nature of network traffic and services require enhanced orchestration and management approaches. While many standard orchestrators and network operators are resulting in an increase of complexity for handling E2E slice orchestration. Besides, there are multiple domains involved in E2E slice orchestration including access, edge, transport and core network each having their specific challenges. Hence, handling of multi-domain, multi-platform and multi-operator based networking environments manually requires specified experts and using this approach it is impossible to handle the dynamic changes in the network at runtime. Also, the manual approaches towards handling such complexity is always error-prone and tedious. Hence, this work proposes an automated and abstracted solution for handling E2E slice orchestration using an intent-based approach. It abstracts the domains from the operators and enable them to provide their orchestration intention in the form of high-level intents. Besides, it actively monitors the orchestrated resources and based on current monitoring stats using the machine learning it predicts future utilization of resources for updating the system states. Resulting in a closed-loop automated E2E network orchestration and management system.

• Journal of the Korea Computer Graphics Society
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• v.30 no.3
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• pp.171-178
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• 2024

Exercises using a Balance Board (BB) are effective in developing balance, strengthening core muscles, and improving physical fitness and concentration. In particular, the Smart Balance Board (SBB), which integrates with various digital content, provides appropriate feedback compared to traditional balance boards, maximizing the effectiveness of the exercise. However, most systems only offer visual and auditory feedback, failing to evaluate the impact on user engagement, interest, and the accuracy of exercise postures. This study proposes an Immersive Smart Balance Board (I-SBB) that utilizes multiple sensors to enable training with various feedback mechanisms and precise postures. The proposed system, based on Arduino, consists of a gyro sensor for measuring the board's posture, a communication module for wired/wireless communication, an infrared sensor to guide the user's foot placement, and a vibration motor for tactile feedback. The board's posture measurements are smoothly corrected using a Kalman Filter, and the multi-sensor data is processed in real-time using FreeRTOS. The proposed I-SBB is shown to be effective in enhancing user concentration and engagement, as well as generating interest, by integrating with diverse content.

• Journal of the Korea Society of Computer and Information
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• v.16 no.7
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• pp.1-11
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• 2011

Many researchers have studied on the methods to improve the processor performance. However, high integrated semiconductor technology for improving the processor performance causes many problems such as battery life, high power density, hotspot, etc. Especially, as hotspot has critical impact on the reliability of chip, thermal problems should be considered together with performance and power consumption when designing high-performance processors. To alleviate the thermal problems of processors, there have been various researches. In the past, mechanical cooling methods have been used to control the temperature of processors. However, up-to-date microprocessors causes severe thermal problems, resulting in increased cooling cost. Therefore, recent studies have focused on architecture-level thermal-aware design techniques than mechanical cooling methods. Even though architecture-level thermal-aware design techniques are efficient for reducing the temperature of processors, they cause performance degradation inevitably. Therefore, if the mechanical cooling methods can manage the thermal problems of processors efficiently, the performance can be improved by reducing the performance degradation due to architecture-level thermal-aware design techniques such as dynamic thermal management. In this paper, we analyze the cooling efficiency of high-performance multicore processors according to mechanical cooling methods. According to our experiments using air cooler and liquid cooler, the liquid cooler consumes more power than the air cooler whereas it reduces the temperature more efficiently. Especially, the cost for reducing $1^{\circ}C$ is varied by the environments. Therefore, if the mechanical cooling methods can be used appropriately, the temperature of high-performance processors can be managed more efficiently.

• Journal of IKEEE
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• v.12 no.4
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• pp.246-254
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• 2008

This paper represents a design of a 4 way SIMD processor with multi-thread and dual phase instruction pipeline. 8 threads can be performing in round-robin order, so any hazards can’t occur. The dual phase pipeline makes a pipeline operate as two pipelines, and it can fetch maximum 4 unit instructions at once. This variable length instruction set divide into first phase and second phase instructions, and with this function, complex branch and addressing can be executed at one clock cycle. This processor reduces the code size to quarter, pull out the doubled performance improvement than normal SIMD architecture.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.493-496
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• 2009

Many AR (Augmented Reality) applications have been interested in a marker-less tracking since the tracking methods give camera poses without attaching explicit markers. In this paper, we propose a new marker-less page recognition and tracking algorithm for an AR book application such as DigilogBook. The proposed method only requires orthogonal images of pages, which need not to be trained for a long time, and the algorithm works in real-time. The page recognition is done in two steps by using SIFT (Scale Invariant Feature Transform) descriptors and the comparison evaluation function. And also, the method provides real-time tracking with 25fps ~ 30fps by separating the page recognition and the frame-to-frame matching into two multi-cores. The proposed algorithm will be extended to various AR applications that require multiple objects tracking.

• Journal of Korea Game Society
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• v.9 no.5
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• pp.43-52
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• 2009

This paper analyzes the four game physics engines in terms of real time techniques. Real time physics is the technology that simplifies the physics-based simulation to apply for the real time applications such as game. Our study includes two commercial physics engines, Havok's Physics SDK and NVIDIA's PhysX SDK, and two open source projects, Open Dynamics Engine and Bullet physics engine. As a result, most of them covers rigid body dynamics and some include either deformable body simulation or fluids simulation, or both. For real time simulation, they adopt the simplified numerical methods, the effective in collision detection/response, and also use the parallel processing hardwares, i.e., multi core CPU, Physics processing unit(PPU), or graphics processing unit(GPU).

• IEMEK Journal of Embedded Systems and Applications
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• v.4 no.2
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• pp.55-62
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• 2009

The power consumption of a high-end microprocessor increases very rapidly. High power consumption will lead to a rapid increase in the chip temperature as well. If the temperature reaches beyond a certain level, chip operation becomes either slow or unreliable. Therefore various approaches for Dynamic Thermal Management (DTM) have been proposed. In this paper, we propose a learning based temperature prediction scheme for a multi-core system. In this approach, from repeatedly executing an application, we learn the thermal patterns of the chip, and we control the temperature in advance through DTM. When the predicted temperature may go beyond a threshold value, we reduce the temperature by decreasing the operation frequencies of the corresponding core. We implement our temperature prediction on an Intel's Quad-Core system which has integrated digital thermal sensors. A Dynamic Frequency System (DFS) technique is implemented to have four frequency steps on a Linux kernel. We carried out experiments using Phoronix Test Suite benchmarks for Linux. The peak temperature has been reduced by on average $5^{\circ}C{\sim}7^{\circ}C$. The overall average temperature reduced from $72^{\circ}C$ to $65^{\circ}C$.