• Journal of Korean Society of societal Security
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• v.1 no.3
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• pp.77-81
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• 2008

In this paper, we introduce a multi purpose environmental monitoring system developed as a commercially available standard using the technique of hetero-core spliced fiber optic sensor. The monitoring system has been tested and evaluated in a possible outdoor condition in view of the full scaled operation at actual sites to be monitored. Additionally, the developed system in this work conveniently provides us with various options of sensor modules intended for monitoring such physical quantities as displacement, distortion, pressure, binary states, and liquid adhesion. Two channels of optical fiber line were monitored, in each of which three displacement sensor modules were connected in series, in order to examine the performance to a pseudo-cracking experiment in the outdoor situation, and to clarify temperature influences to the system in terms of the coupling of optical connectors and the OTDR stability. The pseudo-cracking experiment successfully observed the actually given cracks by means of calculation based on the detected displacement values and their geometrical arrangement of the used sensor modules. And the robustness to the temperature is verified in the various temperature change.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.63-72
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• 2007

In this paper, we propose a novel reconfigurable coprocessor for multimedia mobile terminals. Because most of multimedia operations require fast operations of large amount of data in the limited clock frequency, it is necessary to enhance the performance of the embedded processor that is widely used in current multimedia mobile terminals. Therefore, we proposed and have designed the coprocessor which had the ability of fast operations of multimedia data. The proposed coprocessor was not only reconfigurable, but also flexible and expandable. The proposed coprocessor has been designed by using VHDL and compared with previous reconfigurable coprocessors and a commercial embedded processor in architecture and speed. As a result of the architectural comparison, the proposed coprocessor had better structure in terms of hardware size and flexibility. Also, the simulation results of DCT application showed that the proposed coprocessor was 26 times faster than a commercial ARM processor and 11 times faster than the ARM processor with fast DCT core.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.722-737
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• 2002

As the number of multimedia applications increases, various protocols and architectures have been proposed to provide QoS(Quality of Service) guarantees in the Internet. Most of these techniques, though, bear inherent contradiction between the scalability and the capability of providing QoS guarantees. In this paper, we propose a protocol, named DQSP(Dynamic QoS Support Protocol), which provides the dynamic resource allocation and admission control for QoS guarantees in a scalable way. In DQSP, the core routers only maintain the per source-edge router resource allocation state information. Each of the source-edge routers maintains the usage information for the resources allocated to itself on each of the network links. Based on this information, the source edge routers perform admission control for the incoming flows. For the resource reservation and admission control, DQSP does not incur per flow signaling at the core network, and the amount of state information at the core routers depends on the scale of the topology instead of the number of user flows. Simulation results show that DQSP achieves efficient resource utilization without incurring the number of user flow related scalability problems as with IntServ, which is one of the representative architectures providing end-to-end QoS guarantees.

• Journal of the Korean Magnetics Society
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• v.17 no.3
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• pp.141-146
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• 2007

A new class of LC-resonator for micro magnetic sensor device was invented and fabricated by means of MEMS technique. The micro LC-resonator consists of a solenoidal micro-inductor with a bundle of soft magnetic microwire cores and a capacitor connected in parallel to the micro-inductor. The core magnetic material is a tiny glass coated $Co_{83.2}B_{3.3}Si_{5.9}Mn_{7.6}$ microwire fabricated by a glasscoated melt spinning technique. The core materials were annealed at various temperatures $150^{\circ}C,\;200^{\circ}C\;,250^{\circ}C\;,$ and $300^{\circ}C$ for 1 hour in a vacuum to improve soft magnetic properties. The solenoidal micro-inductors fabricated by MEMS technique were $500{\sim}1,000{\mu}m$ in length with $10{\sim}20$ turns. The changes of inductance as a function of external magnetic field in micro-inductors with properly annealed microwire cores were varied as much as 370%. Since the permeability of ultra soft magnetic microwire is changing rapidly as a function of external magnetic field. The inductance ratio as well as magnetoimpedance ratio (MIR) in a LC-resonator was varied drastically as a function of external magnetic field. The MIR curves can be tuned very precisely to obtain maximum sensitivity. A prototype magnetic sensor device consisting of the developed microinductors with a multivibrator circuit was test successfully.

• Journal of Korea Multimedia Society
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• v.12 no.2
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• pp.200-208
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• 2009

JBIG2, as the next generation standard for binary image compression, must be designed in hardware modules for the JBIG2 FAX to be implemented in an embedded equipment. This paper proposes a hardware module of the high-speed Huffman coder for JBIG2. The Huffman coder of JBIG2 uses selectively 15 Huffman tables. As the Huffman coder is designed to use minimal data and have an efficient memory usage, high speed processing is possible. The designed Huffman coder is ported to Virtex-4 FPGA and co-operating with a software modules on the embedded development board using Microblaze core. The designed IP was successfully verified using the simulation function test and hardware-software co-operating test. Experimental results shows the processing time is 10 times faster than that of software only on embedded system, because of hardware design using an efficient memory usage.

• Journal of KIISE
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• v.42 no.12
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• pp.1623-1628
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• 2015

As the performance of mobile devices has increased, high-end multicore CPUs have become the norm in smartphones. However, such high performance devices are exposed to the problem of battery depletion due to the energy consumption caused by software performance, and despite increases in battery capacity. The required resources are dynamic and varied, and further user interaction is highly random; thus, Linux-based power management such as DVFS is needed to fulfill requirements. In order to reduce power consumption, we propose a method to restrict the CPU frequency of data download while maintaining user reactivity. This can supplement the weakness of existing Linux-based power management techniques like DVFS in relation to webpage loading. Through the implementation of our method at the application level, we confirm that energy consumption from webpage loading is reduced.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1076-1087
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• 2010

Together with a new advent of embedded processor developed to support specific application area and it evolution, a new research of software development to support the embedded processor and its commercial challenge has been revitalized. Retargetability is typically achieved by providing target machine information, ADL, as input. The ADLs are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, assembler, profiler, and debugger. The EXPRESSION ADL follows a mixed level approach-it can capture both the structure and behavior supporting a natural specification of the programmable architectures consisting of processor cores, coprocessors, and memories. And it was originally designed to capture processor/memory architectures and generate software toolkit to enable compiler-in-the-loop exploration of SoC architecture. In this paper, we designed the class-based ADL based on the EXPRESSION ADL to promote the write-ability, extensibility and verified the validation of grammar. For this works, we defined 6 core classes and generated the EXPRESSION's compiler and simulator through the MIPS R4000 description.

• Journal of the Korea Society of Computer and Information
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• v.12 no.6
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• pp.21-30
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• 2007

Simulation means modeling structures or behaviors of the various objects, and experimenting them on the computer system. And the major approaches are DEVS(Discrete Event Systems Specification). Petri-net or Automata and so on. But, the simulation problems are getting more complex or complicated these days, so that an intelligent agent-based is being studied. In this paper, we are describing an intelligent agent-based simulation tool, which can supports the simulation experiment more efficiently. The significances of our system can be described as follows. First, the system can provide some AI algorithms through the system libraries. Second, the system supports simple method of designing the simulation model, since it's been built under the Finite State Machine (FSM) structure. And finally, the system acts as a simulation framework by supporting user not only the simulation engine, but also user-friendly tools, such as modeler scriptor and simulator. The system mainly consists of main simulation engine, utility tools, and some other assist tools, and it is tested and showed some efficient results in the three different problems.