• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.2
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• pp.73-78
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• 2023

The dining philosophers problem(DPP) is that five philosophers sit around a round table and eat spaghetti(or noodles) together, where they must have a pair of chopsticks(two) on both sides of them to eat, and if all philosophers have one chopstick on the right, no one can eat because the deadlock occurs. Deadlocks are a problem that frequently occur in parallel systems, and most current operating systems(OS) cannot prevent it. This paper proposes a silver bullet that causes no deadlock in an OS where all processors of 2≤n≤∞ have multiple parallel processing capabilities. The proposed method is a group round-robin method in which ⌊n/2⌋ odd processors form a group and perform simultaneously, and shift right to the next processor when execution ends. The proposed method is to perform two times for even processors, three times for odd processors per one round-robin. If the proposed method is performed n times, even-numbered processors perform n/2 times and odd-numbered processors perform (n-1)/2-times.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.1095-1104
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• 2010

This study is to suggest the design generation methodology for the maximization of idea generation ability and to overcome restriction of thinking out of existing idea generation methodology, it has suggested the CGS(Character Generation System) that is a creative idea generation methodology identified and complemented the problem of the existing computerized idea generation(PDS with Proportion) method out of the preceded studies on the creative idea generation methodologies. In addition, this research being extended on the article vol.11,no.11, "CGS System based on Three-Dimensional Character Modeling Ⅰ(Part1: about Non-Digital Process )," on Korea Multimedia Society in November 2008 issue and this study is expected to have effectives as one method for idea generation or creative image generation assistance during the 3D character development process with practical implementation of system, research directions and present the results.

• Proceedings of the Korea Contents Association Conference
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• 2009.05a
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• pp.17-22
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• 2009

DaVinci processors are popular media processors for implementing embedded multimedia applications. They support dual core architecture: ARM9 core for video I/O handling as well as system management and peripheral handling, and DSP C64+ core for effective digital signal processing. In this paper, we propose our efforts for optimal implementation of object tracking algorithm in DaVinci-based smart camera which is being designed and implemented by our laboratory. The smart camera in this paper is supposed to support object detection, object tracking, object classification and detection of intrusion into surveillance regions and sending the detection event to remote clients using IP protocol. Object tracking algorithm is computationally expensive since it needs to process several procedures such as foreground mask extraction, foreground mask correction, connected component labeling, blob region calculation, object prediction, and etc. which require large amount of computation times. Thus, if it is not implemented optimally in Davinci-based processors, one cannot expect real-time performance of the smart camera.

• Journal of the Korea Computer Industry Society
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• v.2 no.8
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• pp.1133-1138
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• 2001

In this paper, we implemented that MMT(Multimedia Terminal) demonstrates spot news, weather forecast, sports news and cultural news employed CDMA mobile communication networks. The MMT displays mobile pictures/joint pictures/on screen ad and to make known Bus stop or Mobile stations. The MMT gives driver's and passenger's safety and valuable information for one's use GPS satellites. We verified to make real time mobile picture transfer use of CDMA2000 1×(IS-95C) network and development the scheduler control each module. This system tested on vehicle that train and bus. MMT was implemented high reliability and stability by the embedded system. The mobile terminal shows reliable data transfer rate about 74Kbps on IS-95C.

• Journal of Broadcast Engineering
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• v.20 no.5
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• pp.774-777
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• 2015

This paper introduces the world's first programmable video-processing platform for the enhancement of the video quality of the 8K(7680x4320) UHD(Ultra High Definition) TV operating up to 60 frames per second. In order to support required computing capacity and memory bandwidth, the proposed platform implemented several key features such as symmetric multi-cluster architecture for parallel data processing, a ring-data path between the clusters for data pipelining and hardware accelerators for computing filter operations. The proposed platform based on RP(Reconfigurable Processor) processes video quality enhancement algorithms and handles effectively new UHD broadcasting standards and display panels.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.1
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• pp.17-24
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• 2013

In this paper, we present a multi-core processor including multimedia specific instructions to process multimedia data efficiently in the mobile environment. Multimedia specific instructions exploit subword level parallelism (SLP), while the multi-core processor exploits data level parallelism (DLP). These combined parallelisms improve the performance of multimedia processing applications. The proposed multi-core processor including multimedia specific instructions is implemented and tested using a Xilinx ISE 10.1 tool and SoCMaster3 testbed system including Vertex 4 FPGA. Experimental results using a fire detection algorithm show that multimedia specific instructions outperform baseline instructions in the same multi-core architecture in terms of performance (1.2x better), energy efficiency (1.37x better), and area efficiency (1.23x better).

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2783-2787
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• 2002

최근 멀티미디어 및 통신의 발달로 인하여 영상 정보를 이용한 응용시스템이 많이 연구되고있다. 중간 전달 매체를 이용한 응용시스템으로의 영상 정보를 전달과정에서 잡영(noise) 이 포함되어 시스템의 성능을 저하시키게 된다. 또한 잡영은 임의의 형태이기 때문에 상황에 따라 적합한 필터를 선택하기는 쉽지 않다. 본 논문에서는 유전자 알고리즘 프로세서를 이용하여 필터들의 구성 및 파라미터를 조절하여 임의의 잡영에 진화적응적인 능력을 가지는 영상 전처리 필터를 구현하였다. 주파수 영역의 잡영에 대해서는 하드웨어에 적합하고 구현이 용이한 멀티밴드필터(Multi-Band filter)를 설계하여 사용하였다. 시스템은 유전자알고리즘과 필터블록에 대해서는 하드웨어(FPCA)로 구현하였고 적합도 평가는 PC 기반으로 수행하였다. 실험결과 순수 PC기반의 시뮬레이션에 비해 속도향상 및 성능면에서도 만족할 만한 결과를 얻었다.

• Journal of KIISE:Computing Practices and Letters
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• v.5 no.3
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• pp.326-335
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• 1999

본 논문은 분산환경에서 객체 공유를 통하여 서로 다른 전문가들의 협력 작업과 개발팀 구성원간에 정보 공유, 상호의존적 업무 수행, 공동의 산출물 생성등의 작업을 지원하는 공유시스템의 설계 및 구현에 관한 것이다. 분산 공유 시스템은 ITU-T의 멀티미디어 회의 국제 표준인 T.130 시리즈를 근간으로 회의 세션관리, 동적 참여와 발언권 제어를 하는 회의 제어기, 멀티 캐스팅 통신을 지원하는 다자간 통신서비스, 응용프로그램 객체를 공유하게 하는 공유 기법으로 중앙 집중형 구조를 갖는 GUI 공유 방식과 복제 구조를 지원하기 위하여 이벤트 공유 방식을 지원하는 원격제어기가있으며 사용자 정보와 공유시 필요한 정보 관리를 위한 데이터베이스 프로세서로 구성되어 있다. 따라서 각 구성요소에 대한 설명과 전송량이 많은 GUI공유기에서 시스템 성능 향상의 주된요소인 네트워크 부하를 줄이는 셀(cell)단위의 전송 메커니즘에 대하여 기술하고 있다.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.04a
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• pp.18-19
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• 2014

멀티프로세서 시스템 온칩 (MPSoC) 플랫폼은 고성능 임베디드 시스템을 위한 핵심 구성요소이다. MPSoC 를 구성하는 각각의 처리요소 (processing element, PE)는 대응하는 태스크의 연산 특징에 맞춤으로 최적화되어 있어야 한다. 갈수록 증가하는 고성능의 요구에 따라 동종 MPSoC 는 각각의 태스크 연산 특징에 최적화된 다양한 PE 를 보유한 이기종 MPSoC 로 발전되어 왔다. 따라서 이기종 MPSoC 의 코어들은 응용에 특화된 맞춤형 명령어 세트로 설계된다. 하지만 이러한 이기종성은 다양한 태스크로 구성된 응용들을 어떻게 서로 다른 특성을 지닌 PE 들에 매핑해야 최적의 시스템을 구성할 지를 결정해야 하는 부담을 컴파일러와 같은 툴에 지우고 있다. 잘못된 매핑은 시스템 성능을 현저히 저하시킬 소지가 있다. 본 연구에서는 멀티미디어 응용 태스크의 연산 패턴을 분석하여 최적의 태스크 매핑을 결정하는 기법을 제안하고 있다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.83-90
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• 2004

In this paper, we proposed a new instruction set(X32Y ISA) with 3 different types of instruction mode. The proposed instruction set organizes 32-bit, 24-bit, 16-bit instruction in order to solves a problem of memory size limitation in an embedded microprocessor. We designed a 32-bit 5 stage pipeline RISC microprocessor based on the X32V ISA. To verify the proposed the X32V ISA and a microprocessor, we estimated a program code size of multimedia application programs using a X32V simulator. In result, we verified that the Light mode and the Ultra Light mode obtains 8%, 27% reduction of a program code size through comparison with the Default mode. The proposed microprocessor was verified all X32V instructions execution at Xilinx FPGA with 33MHz operating frequency,