• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1959-1968
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• 2016

The recent automobiles, a number of ECU inside the vehicle has been used. Also, each ECU is connected to different types of networks in accordance with the characteristics. Therefore, efficient data exchange between discrete network has emerged as a very important element. The gateway is responsible for the ability to exchange data between discrete network. In this study, we propose the new gateway algorithm to provide the structure of the mapping table to improve the efficiency of data exchange between discrete network. Also it provides a structure of a new gateway algorithm with a function of adjusting the priority of the data to be transmitted to another network arbitrarily. Moreover, the proposed gateway structure may simultaneously convert the transmission data input from a particular network to multiple networks. Another advantage is easy to change the entire data structure only if we change the table structure in the gateway.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2021.10a
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• pp.236-239
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• 2021

With the growth of AI technology, the scale of Knowledge Graphs continues to be expanded. Knowledge Graphs are mainly expressed as RDF representations that consist of connected triples. Many RDF storages compress and transform RDF triples into the condensed IDs. However, if we try to transform a large scale of RDF triples, it occurs the high processing time and memory overhead because it needs to search the large ID mapping table. In this paper, we propose the method of converting RDF triples using Hash-based ID mapping tables with MapReduce, which is the software framework with a parallel, distributed algorithm. Our proposed method not only transforms RDF triples into Integer-based IDs, but also improves the conversion speed and memory overhead. As a result of our experiment with the proposed method for LUBM, the size of the dataset is reduced by about 3.8 times and the conversion time was spent about 106 seconds.

• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.419-430
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• 2007

It is very important to track whether software is properly developed according to requirements. This study suggests a method to track requirements by using a tracking table. In this study, the tracking table indicates why such requirements are included by detailing the content of requests for proposals and proposals. The table also facilitates verification of the consistency between outputs and the integrity by having ID codes of each requirement mapped to each output. Furthermore, as this study was conducted, it was found that some factors were required to be added or supplemented to the outputs at the requirement gathering stage of MaRMI-Ⅲ v.4.0 methodology. Thus, this study seeks to present this additional result along with the enhanced tracking table. By verifying outputs, the tracking table presented in this study will help to reduce all kinds of risks and problems that may occur in software development due to the lack of management of requirements. In addition, the output of the requirement-gathering stage of MaRMI-Ⅲ v.4.0 methodology will be improved/supplemented according to the creation of tracking tables; this will increment the applicability of the MaRMI-III methodology.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.78-87
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• 2013

NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06c
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• pp.45-47
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• 2012

지식기반 사회가 도래하여 기술혁신이 가속화되고, 글로벌 경쟁이 심화됨에 따라 과학기술 R&D 수행에 선행기술 분석의 중요성이 증대하고 있다. 논문과 특허는 이 작업에 있어서 특허 단독으로는 학술 문헌으로 얻어진 기술 정보가 시장 관점에서 어떻게 활용될 수 있는가를 검증하는데 이용될 수 있다는 점에서 의미가 있지만 분류체계 및 데이터 특성이 다른 논문과 특허를 연계하는 연구는 또 다른 이슈와 가치를 지니며, 아직까지 국내 연구가 부족한 상황이다. 따라서 본 연구에서는 상호 주제 해석이 불가능한 논문과 특허의 분류체계를 일원화할 수 있는 매핑 테이블을 생성해서 두 유형의 문서가 상호 연계가 가능한 환경을 만들고자 한다.

• Journal of Internet Computing and Services
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• v.8 no.2
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• pp.95-103
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• 2007

Many techniques have been proposed for mapping from XML to relations, but most techniques did not negotiate the semantics of XML data. The semantics is important to validate storage, query optimization, modification anomaly in process of schema design. Specially, functional dependencies are an important part of database theory, also it is basis of normalization for relational table in BCNF. This paper propose a new technique that reflect functional dependencies to store relation mapped from XML based on XML Schema. The technique can reduce storage redundancy and can keep up content and structure with constraint described by functional dependencies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1418-1425
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• 2009

This paper proposes a novel FTL (Flash Translation Layer) algorithm based on sector-level mapping to reduce the number of total erase operations in flash memory accesses. The proposed algorithm can reduce the number of erase operations by utilizing the sector-level mapping table when writing data at flash memory. Sector-level mapping technique reduces flash memory access time and extendsthe life time of the flash memory. In the algorithm, wear-leveling is implemented by selecting victim blocks having the minimal number of erase operations, when empty spaces for write are not available. To evaluate the performance of the proposed FTL algorithm, experiments were performed on several applications, such as MP3 players, MPEG players, web browsers and document editors. The proposed algorithm reduces the number of erase operations by 72.4% and 61.9%, when compared with well-known BAST and FAST algorithms, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10c
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• pp.550-552
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• 2004

분산 해시 테이블 (Distributed Hash Table) 을 사용한 P2P 시스템에서는 해시함수를 사용하며 파일과 노드의 ID를 정의하고 파일의 ID와 매핑 (mapping) 되는 ID를 가진 노드에 파일을 저장함으로써 시스템 전체에 파일을 완전히 분산시킨다. 이러한 시스템에서는 파일을 찾을 때 해시된 파일 ID로 찾기 때문에 정확한 매치 (exact match) 만 가능하다. 하지만 현재 P2P 파일 공유 시스템에서는 파일의 전체 이름을 정확히 알지 못하더라도 부분적인 키워드로 파일을 검색할 수 있도록 하는 키워드 검색 (keyword search) 이 요구된다. 본 논문에서는 분산 해시 테이블을 기반으로 하는 P2P 시스템에서 키워드 검색이 가능하도록 하는 방안을 제안한다.

• Proceedings of the Korea Information Processing Society Conference
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• 2008.05a
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• pp.261-264
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• 2008

객체 중심의 개발방법은 오브젝트(Object)를 중심으로 프로세스를 표현하고 있으며, 이에 반해 관계형 DBMS 로 표현 되는 데이터 영역에서는 테이블(Table)을 기반으로 데이터를 집합체로 제시하고 있다. 이러한 차이로 인해 상호 영역이 맺어지는 영구 저장 영역(Persistence Layer)의 구현과 유지보수에 어려움을 겪고 있다. 최근 대두된 Object-Relation Mapping(ORM) 기술은 이러한 영구 저장 영역의 구현을 상대적으로 쉽고 빠르게 해 준다고 하나 이 또한 기술 적용의 어려움과 테이블의 조합으로 만들어지는 조회와 같은 주요 아키텍처 품질 요소를 만족시키기가 어렵다. 이에 본 논문에서는 영구 저장 영역을 ORM 으로 설계하는 데 있어 고려해야 할 요소들을 정리하여 시스템 별로 적절한 아키텍처 선정에 참조할 수 있는 기준을 제시하였다. 또한 이동통신사의 실제 비즈니스 사례를 들어 ORM 이 적용되지 않은 시스템을 대상으로 제안한 기준에 의해 해당 아키텍처를 선정하고 구현하였으며, 적용 전과 적용 후를 비교하여 주요 요구사항을 만족시키는지 평가하였다.

• Proceedings of the CALSEC Conference
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• 2001.08a
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• pp.651-658
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• 2001

□결론 ☆재사용 가능한 클래스는 재사용. ☆많은 클래스들이 EJB의 두 가지 성격을 내포하고 있어서 클래스 분해가 필요. ☆빈 추출 단계 제시. ☆빈 매핑 테이블 제시. ☆사례연구로 채팅 시스템 구현. □향후 연구과제 ☆기존 시스템에서의 컴포넌트 식별 ☆인터페이스 설계에 대한 연구 ☆빈 명세서에 대한 구체적인 구성요소 연구 ☆구현시 문제점 분석(중략)