• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.6
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• pp.3680-3684
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• 2015

A deck crane is installed on the deck of a ship by lifting method using tower crane or floating crane. The safety assessment for two points lifting method should be preceded to ensure a safe installation of deck crane. In this study, finite element models of deck crane and fixing jig are generated for the structural analysis which can evaluate a safety of lifting method. Also, reaction forces and boundary conditions considering lifting state are applied to the structural analysis. The proposed safety assessment method can be useful as an analytic tool that can provide a safer procedure for installation of deck crane by lifting method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.97-104
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• 2004

This paper proposes an efficient VLSI architecture of 9-7/5-3 Lifting DWT filters that is used by lossy or lossless compression of JPEG2000. The proposed architecture uses only internal line memories to compute Lifting-DWT operations and its PE(Processing Element) has critical path with 1 multiplier and 1 adder. To reduce the number of PE, we make the vertical filter that is responsible for the column operations of the first level perform both the row and column operations of the second and following levels. As a result, the architecture has smaller hardware cost compared to that of other architectures. It was modeled in RTL level using VHDL and implemented on Altera APEX 20K FPGA.

• Journal of Korea Multimedia Society
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• v.13 no.7
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• pp.943-949
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• 2010

This paper presents some improvements on VLSI implementation of lifting-based 9/7 wavelet transform by optimization hardware multiplication. The proposed solution requires less logic area and power consumption without performance loss compared to previous wavelet filter structure based on lifting scheme. This paper proposes a better approach to the hardware implementation using Lefevre algorithm based on extensions of Pattern search methods. To compare the proposed structure to the previous solutions on full multiplier blocks, we implemented them using Verilog HDL. For a hardware implementation of the two solutions, the logical synthesis on 0.18 um standard cells technology show that area, maximum delay and power consumption of the proposed architecture can be reduced up to 51%, 43% and 30%, respectively, compared to previous solutions for a 200 MHz target clock frequency. Our evaluation show that when design VLSI chip of lifting-based 9/7 wavelet filter, our solution is better suited for standard-cell application-specific integrated circuits than prior works on complete multiplier blocks.

• Journal of Korea Multimedia Society
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• v.15 no.1
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• pp.81-86
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• 2012

This paper presents a VLSI design for lifting-based discrete wavelet transform (DWT) 9/7 filter using multiplierless multiple constant multiplication (MCM) architecture. This proposed design is based on the lifting scheme using pattern search for folded architecture. Shift-add operation is adopted to optimize the multiplication process. The conventional serial operations of the lifting data flow can be optimized into parallel ones by employing paralleling and pipelining techniques. This optimized design has simple hardware architecture and requires less computation without performance degradation. Furthermore, hardware utilization reaches 100%, and the number of registers required is significantly reduced. To compare our work with previous methods, we implemented the architecture using Verilog HDL. We also executed simulation based on the logic synthesis using $0.18{\mu}m$ CMOS standard cells. The proposed architecture shows hardware reduction of up to 60.1% and 44.1% respectively at 200 MHz clock compared to previous works. This implementation results indicate that the proposed design performs efficiently in hardware cost, area, and power consumption.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.5C
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• pp.344-354
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of $1024{\times}1024$, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using $0.35{\mu}m$ CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7C
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• pp.647-657
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• 2005

In this paper, we proposed a new lifting architecture for JPEG2000 and implemented to ASIC. We proposed a new cell to execute unit calculation of lifting using the property of lifting which is the repetitious arithmetic with same structure, and then recomposed the whole lifting by expanding it. After the operational sequence of lifting arithmetic was analyzed in detail and the causality was imposed for implementation to hardware, the unit cell was optimized. A new lifting kernel was organized by expanding simply the unit cell, and a lifting processor was implemented for Motion JPEG2000 using it. The implemented lifting kernel can accommodate the tile size of 1024$\times$1024, and support both lossy compression using the (9,7) filter and lossless compression using (5,3) filter. Also, it has the same output rate as input rate, and can continuously output the wavelet coefficients of 4 types(LL, LH, HL, HH) at the same time. The implemented lifting processor completed a course of ASIC using 0.35$\mu$m CMOS library of SAMSUNG. It occupied about 90,000 gates, and stably operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the improved operated in about 150MHz though difference from the used macro cell for the multiplier. Finally, the performance can be identified in comparison with the previous researches and commercial IPs.

• Journal of Ocean Engineering and Technology
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• v.16 no.1
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• pp.71-75
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• 2002

대형 시추구조물의 건조는 보통 드라이도크에서 하거나, 해양에서 선체와 데크를 접합하는 방법을 사용한다. 그러나 적당한 해양 접합장소가 없거나 드라이도크의 공간부족으로 현대중공업에서는 드라이도크나 해양에서의 접합건조 대신 부유식 시추구조물을 지상에서 조립하는 방법을 채택하게 되었다. 현대중공업에서는 세 가지 단계를 통해 지상 데크조립을 수행하였다. 첫 번째는 네 개의 철골구조 리프팅타워 상에서 유압리프팅시스템을 이용하여 데크를 지상으로부터 38m 들어올린다. 두 번째는 마찰을 줄이기 위해 윤활제가 칠해진 합성 플라스틱으로 싸인 미끄럼틀(Skidway)을 이용하여 두 개의 6000톤 짜리 하부구조를 데크 아래로 끌어 들인다. 마지막 단계로 데크와 하부구조를 단단히 결합시킨다. 이 과정에 2주일이 소요되었으며 일련의 작업을 거쳐 중량 25,500톤급의 Deepwater Nautilus (RBS-8M) 시추선을 무사히 바다 위로 인도하였다. RBS-8M의 데크결합에 Super Lift를 적용하여 성공시킨 사례를 통해 현대중공업의 초대형 시추구조물 건조방식이 이상적이고, 작업 공기나 원가 측면에서 우위가 있음을 시사하고 있으며 이렇게 건조작업의 대부분을 지상에서 수행한 과정을 통해 작업관리, 품질관리, 일정관리에도 좋은 결과를 가져올 수 있었다.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• Journal of Broadcast Engineering
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• v.11 no.2 s.31
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• pp.164-173
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• 2006

The data structure of the concentric mosaic can be regarded as a video sequence with a slowly panning camera. We take a concentric mosaic with match or alignment of video sequences. Also the concentric mosaic required for huge memory. Thus, compressing is essential in order to use the concentric mosaic. Therefore we need the algorithm that compressed data structure was maintained and the scene was decoded. In this paper, we used 3D lifting transform to compress concentric mosaic. Lifting transform has a merit of wavelet transform and reduces computation quantities and memory. Because each frame has high correlation, the complexity which a scene is detected form 3D transformed bitstream is increased. Thus, in order to have higher performance and decrease the complexity of detecting of a scene we executed 3D lifting and then transformed data set was sequently compressed with each frame unit. Each frame has a flexible bit rate. Also, we proposed the algorithm that compressed data structure was maintained and the scene was decoded by using property of lifting structure.