• Korean Journal of Materials Research
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• v.6 no.11
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• pp.1146-1152
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• 1996

실제 사용시 신뢰성을 보장하기 위하여, 고온에서 장시간 동안의 시효로 인한 ACA COG(Anisotropic Conductive Chip On Glass) 접합 특성의 변화가 연구되었다. 모든 접합 시편들은 16$0^{\circ}C$에서 156시간 동안 유지되었고 시효하는 동안의 접촉저항의 변화는 감소하였다. 특히, 156시간이후, 4000개 /$\textrm{mm}^2$의 입자밀도를 가진 ACA에서는 접촉저항의 벼노하가 나타나지 않았다. 입자크기의 경우 작은 입자를 가진 ACA는 16$0^{\circ}C$에서 시효후에도 접촉저항의 변화를 보이지 않았다. 또한 4000개/$\textrm{mm}^2$ 및 5$\mu\textrm{m}$ 입자를 가진 ACA를 사용한 시편은 접합상태가 안정하였기 때문에 16$0^{\circ}C$에서도 경화수지의 팽창 및 리플로우(reflow)에 의한 영향을 받지 않았다. 따라서 이 ACA에서는 16$0^{\circ}C$에서 156시간 동안 시효한 후에도 오픈(open)이 나타나지 않았다.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.677-680
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• 2004

통상적인 언어 처리의 분석 과정은 전처리, 형태소분석, 품사 태깅, 복합 단위 인식, 구문 분석, 그리고 의미 분석 등의 여러 단계로 이루어진다. 분석의 매 단계에서 중의성(Ambiguity)가 발생하며, 이를 해결하기 위한 노력으로 구문 분석 이전의 분석 단계에서도 정확률(Precision)을 높이기 위해, 어휘(Lexical) 정보, 품사정보 그리고 구문 정보 등을 이용한다. 각 단계에서 고급 정보로서의 구문 정보 이용은 구문분석의 중복성과 분석 지식의 중복성을 야기한다. 또한, 기존의 처리 흐름에서는 각 분석 단계에서의 결과는 최종적인 것으로, 이로 인해 다음 분석 단계에 분석 오류를 전파한다. 본 논문에서는 구문 분석기를 분석 결과의 최종 판단자로 이용할 것을 제안한다. 즉, 구문 분석 전단계의 모든 분석 정보는 구문 분석기에 제공되고, 구문분석기는 상향식 구문분석을 수행하면서 이들 정보들로부터 최종의 그리고 최적의 분석 후보를 결정한다. 이를 위해 구문분석기는 한 문장 단위를 입력 받는 기존의 제한을 따르지 않는다. 제안된 방법은 구문분석 앞 단계에서의 잘못된 정보 제공(예: 문장 분리 오류, 품사 오류, 복합단위 인식 오류 등)으로부터 자유로우며, 이를 통해 분석 실패의 가능성을 최대로 줄인다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2019.07a
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• pp.151-152
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• 2019

운동 기구를 이용한 운동의 경우 바른 자세와 균형을 유지하는 것이 중요하다. 이에 본 논문에서는 적외선 감지센서가 부착된 디스플레이형 전신거울과 프리웨이트 운동기구에 부착된 센서를 이용하여 이용자의 정보를 인지하고 디스플레이 장치에 출력되는 가상 트레이너를 통해 균형 운동에 대한 가이드를 제공하는 게임형 콘텐츠를 설계하였다. 본 콘텐츠의 목표는 운동 시에 중요한 바른 자세를 잡기 위하여 균형 상태를 알 수 있게 하며, 가상트레이너에 의해 보다 효과적이고 흥미로우며 지속적인 운동을 가능하게 하는 방법을 제공하는 것에 있다.

• Journal of Auto-vehicle Safety Association
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• v.15 no.1
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• pp.7-15
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• 2023

The purpose of this study is to predict the dynamic behavior of clamshell hood system on the harsh road driving condition, and secure the safety and durability performance of the system. The equation of motion of hood system is derived and the numerical analysis is implemented to obtain the lateral movement of the hood system. Also, the actual Belgian road test results are correlated to the predicted ones, and confirm the reliability of the system. Then, the parameter study is conducted to figure out the sensitive factors to affect the dynamic behavior, and the engineering design guide to make the system robust to confine the minimum friction force generated from hood latch and maximum hood weight is suggested from this research.

• Journal of the Korea Convergence Society
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• v.10 no.12
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• pp.53-61
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• 2019

The risk of project failure has increased recently as ERP systems have been transformed into Web environments and task complexity has increased. Although low-code platform development tools are being used as a way to solve this problem, limitations exist as they are centered on UI. To overcome this, back-end development tools are required that can be developed quickly and easily, not only from the front development but also from a variety of development sources produced from the ERP development process, including back-end business services. In addition, the development tools included within existing ERP products require a lot of learning time from the perspective of beginner and intermediate developers due to high entry barriers. To address these shortcomings, this paper seeks to study ways to overcome the limitations of existing development tools within the ERP by providing customized development tool functions by enhancing the usability of ERP development tools suitable for each developer's skills and roles based on the requirements required by ERP development tools, such as reducing the time required for querying, automatic binding of data for testing for service-based units, and checking of source code quality.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.2
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• pp.37-45
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• 2008

In this study, reliabilities of Cu (60 um)/SnAg (20 um) double-bump flip chip assemblies were investigated for the flip chip interconnections on organic substrates with 100 um pitch. After multiple reflows at $250^{\circ}C\;and\;280^{\circ}C$, bump contact resistances were almost same regardless of number of reflows and reflow temperature. In the high temperature storage test, there was no bump contact resistance change at $125^{\circ}C$ up to 2000 hours. However, bump contact resistances slightly increased at $150^{\circ}C$ due to Kirkendall voids formation. In the electromigration test, Cu/SnAg double-bump flip chip assemblies showed no electromigration until about 600 hours due to reduced local current density. Finally, in the thermal cycling test, thermal cycling failure mainly occurred at Si chip/Cu column interface which was found out the highest stress concentration site in the finite element analysis. As a result, Al pad was displaced out under thermal cycling. This failure mode was caused by normal compressive strain acting Cu column bumps along perpendicular direction of a Si chip.

• The KIPS Transactions:PartA
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• v.12A no.5 s.95
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• pp.451-460
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• 2005

We present a methodology to design energy-efficient data paths using FPGAs. Our methodology integrates domain specific modeling, coarse-grained performance evaluation, design space exploration, and low-level simulation to understand the tradeoffs between energy, latency, and area. The domain specific modeling technique defines a high-level model by identifying various components and parameters specific to a domain that affect the system-wide energy dissipation. A domain is a family of architectures and corresponding algorithms for a given application kernel. The high-level model also consists of functions for estimating energy, latency, and area that facilitate tradeoff analysis. Design space exploration(DSE) analyzes the design space defined by the domain and selects a set of designs. Low-level simulations are used for accurate performance estimation for the designs selected by the DSE and also for final design selection We illustrate our methodology using a family of architectures and algorithms for matrix multiplication. The designs identified by our methodology demonstrate tradeoffs among energy, latency, and area. We compare our designs with a vendor specified matrix multiplication kernel to demonstrate the effectiveness of our methodology. To illustrate the effectiveness of our methodology, we used average power density(E/AT), energy/(area x latency), as themetric for comparison. For various problem sizes, designs obtained using our methodology are on average $25\%$ superior with respect to the E/AT performance metric, compared with the state-of-the-art designs by Xilinx. We also discuss the implementation of our methodology using the MILAN framework.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of the Microelectronics and Packaging Society
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• v.31 no.2
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• pp.69-77
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• 2024

Due to the miniaturization and multifunctionality of electronic devices, a surface mount technology in the form of molded interconnect devices (MID), which directly forms electrodes and circuits on the plastic injection parts and mounts components and parts on them, is being introduced to overcome the limitations in the mounting area of electronic components. However, when using plastic injection parts with low thermal stability, there are difficulties in mounting components through the conventional reflow process. In this study, we developed a process that utilizes induction heating, which can selectively heat specific areas or materials, to melt solder and mount components without causing any thermal damage to the plastic. We designed the shape of an induction heating Cu coil that can concentrate the magnetic flux on the area to be heated, and verified the concentration of the magnetic flux and the degree of heating on the pad part through finite element method (FEM). LEDs, capacitors, resistors, and connectors were mounted on a polycarbonate substrate using induction heating to verify the mounting process, and their functionality was confirmed. We presented the applicability of a selective heating process through magnetic induction that can overcome the limitations of the reflow method.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.7-14
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• 2015

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.