• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.244-250
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• 2012

This paper describes a 4-Gb/s receiver circuit for a low-swing ground-referenced differential signaling system. The receiver employs a common-gate level-shifter and a continuous linear equalizer which compensates inter-symbol-interference (ISI) and improves voltage and timing margins. A bias circuit maintains the bias current of the level-shifter when the common level of the input signal changes. The receiver is implemented with a low-power 65-nm CMOS technology. When 4-Gb/s 400mVp-p signals are transmitted to the receiver through the channel with the attenuation of -19.7dB, the timing margin based on bit error rate (BER) of $10^{-11}$ is 0.48UI and the power consumption is as low as 0.30mW/Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.