• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.432-438
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• 2011

This paper describes an analysis of optimal design conditions of multi-mode LDPC(low density parity check) decoder which supports three block lengths (648, 1296, 1944) and four code rates (1/2, 2/3, 3/4, 5/6) for IEEE 802.11n WLAN system. A fixed-point model of LDPC decoder, which adopts min-sum algorithm and layered decoding scheme, is implemented using Matlab. From fixed-point simulation results for various bit-width parameters such as internal bit-width, integer/fractional part bit-widths, optimal design conditions and decoding performance of LDPC decoder are analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.921-929
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• 2011

This paper describes an analysis of the decoding performance and decoding convergence speed of layered LDPC(low-density parity-check) decoder for mobile WiMAX system, and the optimal design conditions for hardware implementation are searched. A fixed-point model of LDPC decoder, which is based on the min-sum algorithm and layered decoding scheme, is implemented and simulated using Matlab model. Through fixed-point simulations for the block lengths of 576, 1440, 2304 bits and the code rates of 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 specified in the IEEE 802.16e standard, the effect of internal bit-width, block length and code rate on the decoding performance are analyzed. Simulation results show that fixed-point bit-width larger than 8 bits with integer part of 5 bits should be used for acceptable decoding performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.