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High Performance Hardware Implementation of the 128-bit SEED Cryptography Algorithm (128비트 SEED 암호 알고리즘의 고속처리를 위한 하드웨어 구현)

  • 전신우;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.11 no.1
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    • pp.13-23
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    • 2001
  • This paper implemented into hardware SEED which is the KOREA standard 128-bit block cipher. First, at the respect of hardware implementation, we compared and analyzed SEED with AES finalist algorithms - MARS, RC6, RIJNDAEL, SERPENT, TWOFISH, which are secret key block encryption algorithms. The encryption of SEED is faster than MARS, RC6, TWOFISH, but is as five times slow as RIJNDAEL which is the fastest. We propose a SEED hardware architecture which improves the encryption speed. We divided one round into three parts, J1 function block, J2 function block J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined one round into three parts, J1 function block, J2 function block, J3 function block including key mixing block, because SEED repeatedly executes the same operation 16 times, then we pipelined it to make it more faster. G-function is implemented more easily by xoring four extended 4 byte SS-boxes. We tested it using ALTERA FPGA with Verilog HDL. If the design is synthesized with 0.5 um Samsung standard cell library, encryption of ECB and decryption of ECB, CBC, CFB, which can be pipelined would take 50 clock cycles to encrypt 384-bit plaintext, and hence we have 745.6 Mbps assuming 97.1 MHz clock frequency. Encryption of CBC, OFB, CFB and decryption of OFB, which cannot be pipelined have 258.9 Mbps under same condition.

Design of a Secure Web-mail System based on End-to-End (End-to-End 기반의 안전한 웹 메일 시스템 설계)

  • 전철우;이종후;이상호
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.13 no.2
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    • pp.13-29
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    • 2003
  • Web-mail system is worthy of note as a next generation e-mail system for its mobility and easiness. But many web-mail system does not have any kind of security mechanism. Even if web-mail system provides security services, its degree of strength is too low. Using these web-mail systems, the e-mail is tabbed, modified or forged by attacker easily. To solve these problems, we design and implement secure web-mail system based on the international e-mail security standard S/MIME in this thesis. This secure web-mail system is composed of server system and client system The server system performs basic mail functions - sending/receiving the mails, storing the mails, and management of user information, etc. And the client system performs cryptographic functions - encryption/decryption of the mails, digital signing and validation, etc. Because client system performs cryptographic functions this secure web-mail system gives its reliability and safety, and provides end-to-end security between mail users. Also, this secure web-mail system increase system efficiency by minimize server load.

A Method for Detecting the Exposure of an OCSP Responder's Session Private Key in D-OCSP-KIS (D-OCSP-KIS에서 OCSP Responder의 세션 개인키의 노출을 검출하는 방법)

  • Lee, Young-Gyo;Nam, Jung-Hyun;Kim, Jee-Yeon;Kim, Seung-Joo;Won, Dong-Ho
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.15 no.4
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    • pp.83-92
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    • 2005
  • D-OCSP-KIS proposed by Koga and Sakurai not only reduces the number or OCSP Responder's certificate but also criers the certificate status validation about OCSP Responder to the client. Therefore, D-OCSP-KIS is an effective method that can reduce the communication cost, computational time and storage consumption in client, but it has some problems. In case an attacker accidentally acquires an OCSP Responder's session private key in a time period (e.g., one day), she can disguise as the OCSP Responder in the time period unless the OCSP Responder recognizes. She can offer the wrong response to the client using the hash value intercepted. And the server and user on I-commerce can have a serious confusion and damage. And the computation and releasing of hash chain can be a load to CA. Thus, we propose a method detecting immediately the exposure of an OCSP Responder's session private key and the abuse of hash value in D-OCSP-KIS.

Fast RSA Montgomery Multiplier and Its Hardware Architecture (고속 RSA 하드웨어 곱셈 연산과 하드웨어 구조)

  • Chang, Nam-Su;Lim, Dae-Sung;Ji, Sung-Yeon;Yoon, Suk-Bong;Kim, Chang-Han
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.17 no.1
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    • pp.11-20
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    • 2007
  • A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].

Implementation of High-radix Modular Exponentiator for RSA using CRT (CRT를 이용한 하이래딕스 RSA 모듈로 멱승 처리기의 구현)

  • 이석용;김성두;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.10 no.4
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    • pp.81-93
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    • 2000
  • In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

Implementation of RSA modular exponentiator using Division Chain (나눗셈 체인을 이용한 RSA 모듈로 멱승기의 구현)

  • 김성두;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.2
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    • pp.21-34
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    • 2002
  • In this paper we propos a new hardware architecture of modular exponentiation using a division chain method which has been proposed in (2). Modular exponentiation using the division chain is performed by receding an exponent E as a mixed form of multiplication and addition with divisors d=2 or $d=2^I +1$ and respective remainders r. This calculates the modular exponentiation in about $1.4log_2$E multiplications on average which is much less iterations than $2log_2$E of conventional Binary Method. We designed a linear systolic array multiplier with pipelining and used a horizontal projection on its data dependence graph. So, for k-bit key, two k-bit data frames can be inputted simultaneously and two modular multipliers, each consisting of k/2+3 PE(Processing Element)s, can operate in parallel to accomplish 100% throughput. We propose a new encoding scheme to represent divisors and remainders of the division chain to keep regularity of the data path. When it is synthesized to ASIC using Samsung 0.5 um CMOS standard cell library, the critical path delay is 4.24ns, and resulting performance is estimated to be abort 140 Kbps for a 1024-bit data frame at 200Mhz clock In decryption process, the speed can be enhanced to 560kbps by using CRT(Chinese Remainder Theorem). Futhermore, to satisfy real time requirements we can choose small public exponent E, such as 3,17 or $2^{16} +1$, in encryption and verification process. in which case the performance can reach 7.3Mbps.

A Novel Redundant Binary Montgomery Multiplier and Hardware Architecture (새로운 잉여 이진 Montgomery 곱셈기와 하드웨어 구조)

  • Lim Dae-Sung;Chang Nam-Su;Ji Sung-Yeon;Kim Sung-Kyoung;Lee Sang-Jin;Koo Bon-Seok
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.16 no.4
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    • pp.33-41
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    • 2006
  • RSA cryptosystem is of great use in systems such as IC card, mobile system, WPKI, electronic cash, SET, SSL and so on. RSA is performed through modular exponentiation. It is well known that the Montgomery multiplier is efficient in general. The critical path delay of the Montgomery multiplier depends on an addition of three operands, the problem that is taken over carry-propagation makes big influence at an efficiency of Montgomery Multiplier. Recently, the use of the Carry Save Adder(CSA) which has no carry propagation has worked McIvor et al. proposed a couple of Montgomery multiplication for an ideal exponentiation, the one and the other are made of 3 steps and 2 steps of CSA respectively. The latter one is more efficient than the first one in terms of the time complexity. In this paper, for faster operation than the latter one we use binary signed-digit(SD) number system which has no carry-propagation. We propose a new redundant binary adder(RBA) that performs the addition between two binary SD numbers and apply to Montgomery multiplier. Instead of the binary SD addition rule using in existing RBAs, we propose a new addition rule. And, we construct and simulate to the proposed adder using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is faster by a minimum 12.46% in terms of the time complexity than McIvor's 2 method and existing RBAs.

A Study of Hazard Analysis and Monitoring Concepts of Autonomous Vehicles Based on V2V Communication System at Non-signalized Intersections (비신호 교차로 상황에서 V2V 기반 자율주행차의 위험성 분석 및 모니터링 컨셉 연구)

  • Baek, Yun-soek;Shin, Seong-geun;Ahn, Dae-ryong;Lee, Hyuck-kee;Moon, Byoung-joon;Kim, Sung-sub;Cho, Seong-woo
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.19 no.6
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    • pp.222-234
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    • 2020
  • Autonomous vehicles are equipped with a wide rage of sensors such as GPS, RADAR, LIDAR, camera, IMU, etc. and are driven by recognizing and judging various transportation systems at intersections in the city. The accident ratio of the intersection of the autonomous vehicles is 88% of all accidents due to the limitation of prediction and judgment of an area outside the sensing distance. Not only research on non-signalized intersection collision avoidance strategies through V2V and V2I is underway, but also research on safe intersection driving in failure situations is underway, but verification and fragments through simple intersection scenarios Only typical V2V failures are presented. In this paper, we analyzed the architecture of the V2V module, analyzed the causal factors for each V2V module, and defined the failure mode. We presented intersection scenarios for various road conditions and traffic volumes. we used the ISO-26262 Part3 Process and performed HARA (Hazard Analysis and Risk Assessment) to analyze the risk of autonomous vehicle based on the simulation. We presented ASIL, which is the result of risk analysis, proposed a monitoring concept for each component of the V2V module, and presented monitoring coverage.

Estimation of Pollutant Sources in Dangjin Coal-Fired Power Plant Using Carbon Isotopes (탄소 안정동위원소를 이용한 석탄화력발전소 인근 오염원 기원 추정 : 당진시를 중심으로)

  • Yoon, Soohyang;Cho, Bong-Yeon
    • The Journal of the Korea Contents Association
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    • v.21 no.3
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    • pp.567-575
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    • 2021
  • Residents in Dangjin, South Chungcheong Province, in which large-scale emissions facilities such as coal-fired power plants and steel mills are concentrated, are very much concerned about their health despite the local government's aggressive efforts to improve air quality and reduce greenhouse gases. To understand the impact of coal-fired power plants and external factors on local air pollution, the origins of local pollutants were investigated using stable carbon isotopes that are generally used as tracers of the provenance of fine or ultrafine dust. The origins of the pollutants were analyzed with the data library, built using the seasonally measured data for the two separate locations selected considering the distance from the coal-fired power plant and the analysis of previous studies, and with the back trajectory analysis. As a result of analyzing stable isotope ratios, the tendency of high concentration was found in the order of winter > spring > fall > summer. According to the data matching with the library, the mobile pollutants and open-air incineration had a relatively higher impact on the local air pollution. It is believed that this study, as a pilot study, should focus on securing the reliability of the study results through continuous monitoring and data accumulation.

Accuracy Evaluation of Earthwork Volume Calculation According to Terrain Model Generation Method (지형모델 구축 방법에 따른 토공물량 산정의 정확도 평가)

  • Park, Joon Kyu;Jung, Kap Yong
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.39 no.1
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    • pp.47-54
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    • 2021
  • Calculation of quantity at construction sites is a factor that has a great influence on construction costs, and it is important to calculate accurate values. In this study, topographic model was created by using drone photogrammetry and drone LiDAR to estimate earthwork volume. ortho image and DSM (Digital Surface Model) were constructed for the study area by drone photogrammetry, and DEM (Digital Elevation Model) of the target area was established using drone LiDAR. And through accuracy evaluation, accuracy of each method are 0.034m, 0.35m in horizontal direction, 0.054m, 0.25m in vertical direction. Through the research, the usability of drone photogrammetry and drone LiDAR for constructing geospatial information was presented. As a result of calculating the volume of the study site, the UAV photogrammetry showed a difference of 1528.1㎥ from the GNSS (Global Navigation Satellite System) survey performance, and the 3D Laser Scanner showed difference of 160.28㎥. The difference in the volume of earthwork is due to the difference in the topographic model, and the efficiency of volume calculation by drone LiDAR could be suggested. In the future, if additional research is conducted using GNSS surveying and drone LiDAR to establish topographic model in the forest area and evaluate its usability, the efficiency of terrain model construction using drone LiDAR can be suggested.