• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.6
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• pp.1083-1091
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• 2017

This paper describes a design of cryptographic processor supporting 224-bit elliptic curves over prime field defined by NIST. Scalar point multiplication that is a core arithmetic function in elliptic curve cryptography(ECC) was implemented by adopting the modified Montgomery ladder algorithm. In order to eliminate division operations that have high computational complexity, projective coordinate was used to implement point addition and point doubling operations, which uses addition, subtraction, multiplication and squaring operations over GF(p). The final result of the scalar point multiplication is converted to affine coordinate and the inverse operation is implemented using Fermat's little theorem. The ECC processor was verified by FPGA implementation using Virtex5 device. The ECC processor synthesized using a 0.18 um CMOS cell library occupies 2.7-Kbit RAM and 27,739 gate equivalents (GEs), and the estimated maximum clock frequency is 71 MHz. One scalar point multiplication takes 1,326,985 clock cycles resulting in the computation time of 18.7 msec at the maximum clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.94-104
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• 2008

In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with $250{\mu}m,\;180{\mu}m,\;130{\mu}m$ and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

• Proceedings of the Korea Society for Energy Engineering kosee Conference
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• 2008.04a
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• pp.69-75
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• 2008

기포반응도는 월성발전소를 비롯한 CANDU형 원자로의 주된 안전성 쟁점사안으로 끊임없이 논의되어 왔다. 이는 설계기준사고가 노심에서 열에너지 불균형이 원인이 되어 기준이상의 핵연료 파손과 방사성물질 누출로 발전할 위험이 있는 사건들로 정의될 때, 사건 진행 과정에 기포반응도 증가는 조기에 운전중단을 실패할 경우 출력폭주로 이어지므로 사건의 결말이 중대사고로 전환될 위험이 크기 때문이다. 본 연구는 공개된 최신 핵자료인 ENDF/B-VII.0를 NJOY.99로 처리한 연속에너지 반응단면적 라이브러리를 구축하고 MCNP-4C에 접속하여 37봉 천연우라늄 핵연료다발의 표준노심격자에 대한 기포반응도를 시뮬레이션하여, 지금까지 각종문헌에 제시된 값들과 비교, 종합하므로 내제된 불확실성을 추정하는 내용이다. ENDF/B-VII.0 기반 MCNP-4C의 CANDU 노심격자 모델은 동일한 핵자료와 핵종농도를 사용한 WIMS-IAEA 모델과 비교할 때, 초기 노심의 임계도 오차 약 3.51mk가 연소 진행에 따라 $7.5\times10^{-4}mk$/MWD/teU의 비율로 감소하는 것으로 나타났다. 또한 MCNP-4C 예측기포반응도는 초기노심에서 기포율 50% 및 100%에 대해 각각 8.38 및 15.96mk, 평형노심에서 7.68 및 14.72mk로 계산된다. 이는 월성 2, 3, 4 FSAR의 초기노심 및 평형노심에서 100% 기포상태에 대한 값, 약15.0 및 10.6mk와 비교할 때, 초기노심은 약 1.0mk 평형노심은 약4, 1mk 보수적이지만, 다른 연구결과들과는 최대오차 ${\pm}1{\sim}2mk$ 이내에서 잘 일치하는 것으로 평가되었다. 본 연구는 CANDU 노심의 기포반응도 불확실성 요인의 규명 및 영향평가를 위한 노력의 일부로서 앞으로 감속재의 붕산농도 변화, 감속재 및 냉각재의 중수 순도 변화, 기기노화에 의한 격자 구조 및 물성 변화, 중성자속 및 출력 분포 불균형, 반응도조절장치의 위치, 등 주요 설계변수의 변화에 대한 반응도영향 분석연구를 계속할 계획이다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Resources Recycling
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• v.27 no.1
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• pp.84-91
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• 2018

In this study, a novel soft information based most probable classification scheme is proposed for sorting recyclable metal alloys with laser induced breakdown spectroscopy (LIBS). Regression analysis with LIBS captured spectrums for estimating concentrations of common elements can be efficient for classifying unknown arbitrary metal alloys, even when that particular alloy is not included for training. Therefore, partial least square regression (PLSR) is employed in the proposed scheme, where spectrums of the certified reference materials (CRMs) are used for training. With the PLSR model, the concentrations of the test spectrum are estimated independently and are compared to those of CRMs for finding out the most probable class. Then, joint soft information can be obtained by assuming multi-variate normal (MVN) distribution, which enables to account the probability measure or a prior information and improves classification performance. For evaluating the proposed schemes, MVN soft information is evaluated based on PLSR of LIBS captured spectrums of 9 metal CRMs, and tested for classifying unknown metal alloys. Furthermore, the likelihood is evaluated with the radar chart to effectively visualize and search the most probable class among the candidates. By the leave-one-out cross validation tests, the proposed scheme is not only showing improved classification accuracies but also helpful for adaptive post-processing to correct the mis-classifications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.80-88
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• 2008

In this paper, the block cipher algorithms, 3-DES(Triple Data Encryption Standard), AES(Advanced Encryption Standard), SEED, HASH(SHA-1), which are domestic and international standards, have been implemented as an integrated cryptographic engine for smart card applications. For small area and low power design which are essential requirements for portable devices, arithmetic resources are shared for iteration steps in each algorithm, and a two-level clock gating technique was used to reduce the dynamic power consumption. The integrated cryptographic engine was verified with ALTERA Excalbur EPXA10F1020C device, requiring 7,729 LEs(Logic Elements) and 512 Bytes ROM, and its maximum clock speed was 24.83 MHz. When designed by using Samsung 0.18 um STD130 standard cell library, the engine consisted of 44,452 gates and had up to 50 MHz operation clock speed. It was estimated to consume 2.96 mW, 3.03 mW, 2.63 mW, 7.06 mW power at 3-DES, AES, SEED, SHA-1 modes respectively when operating at 25 MHz clock. We found that it has better area-power optimized structure than other existing designs for smart cards and various embedded security systems.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.