• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.75-82
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• 2008

In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the performance of the first detected symbol which causes error propagation, the proposed algorithm achieves a considerable performance gain as compared to the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In case of 16QAM MIMO-SM system with 4 transmit and 4 receive ($4{\times}4$) antennas, at $BER=10^{-3}$ the proposed algorithm obtains the gai improvement of about 2.5-13.5 dB over the conventional algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.1C
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• pp.112-121
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• 2002

In this paper, we present a design of a hash processor for data security systems. Two standard hash algorithms, Sha-1(American) and HAS-1600(Korean), are implemented on a single hash engine to support real time processing of the algorithms. The hash processor can also be used as a PRNG(Pseudo-random number generator) by utilizing SHA-1 hash iterations, which is being used in the Intel software library. Because both SHA-1 and HAS-160 have the same step operation, we could reduce hardware complexity by sharing the computation unit. Due to precomputation of message variables and two-stage pipelined structure, the critical path of the processor was shortened and overall performance was increased. We estimate performance of the hash processor about 624 Mbps for SHA-1 and HAS-160, and 195 Mbps for pseudo-random number generation, both at 100 MHz clock, based on Samsung 0.5um CMOS standard cell library. To our knowledge, this gives the best performance for processing the hash algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.3C
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• pp.311-321
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• 2009

This paper proposes an efficient frequency offset estimation algorithm for MB-OFDM based UWB systems. The time-frequency interleaving in MB-OFDM extends the time-interval between two transmitted OFDM symbols in the same sub-band. The extended time-interval causes not only the degradation of the system performance by reducing frequency offset estimation range, but also the increase of the hardware complexity by requiring the larger number of storing samples. The proposed estimation algorithm expands the estimation range by applying the proposed sign detection scheme. Simulation results show that the estimation range is increased above 30 ppm compared with a conventional auto-correlation based scheme. The estimation is performed on only one sub-band, and the frequency offsets of the others are calculated by relation to center frequency. This way reduced the number of the storing samples by about l/3. The frequency offset estimator with the proposed algorithm was designed into the architecture which minimizes hardware overhead by time-sharing operators and memory units, and which was synthesized to gate-level circuits using $0.13{\mu}m$ CMOS technology, and the total gates were about 47K.

• Journal of Information Management
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• v.38 no.1
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• pp.141-160
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• 2007

Many contents produced and provided as development of information technology on the internet. Especially discussion that collecting and storing of digital information resources, is expanded as growing dependence on academic information of research workers. Open Access is a new paradigm of information distribution that is opposite concept of high price distribution academic information. It is an OAI system that is intended to collect and automate open access data in good order. This paper constructs stOAI based on OAI that is a science and technology information providing system. This system provides international academic journal free of charge that collect and store through OAI protocol in OA(Open Access) of yesKISTI(science and technology information portal service). Also, It provides automate and centralize science technology information, that KISTI has, to external institution as a standard type.

• Journal of the Korean GEO-environmental Society
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• v.15 no.3
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• pp.57-63
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• 2014

This study has been conducted to building a library intended for structures considered in the design of reclamation for design automation and developing browser for integrated management system. The library has been developed using a parametric modeling method capable of changing section shape, also classifying standard crossing and family library, has been developed according to the working environment. Classified library by the characteristics manages objects and working modeling on based BIM has been developed browser using the C# program for objects to use conveniently. By interworking between developed Browser and 3D Autocad based BIM, it is possible to use easily at design drafting, calculating quantities, developing a new library, and managing a library. The browser using effectively exclusive library to reclamation is developed in this study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.148-156
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• 2001

This paper proposed embedded application-specific microprocessor(YS-RDSP) whose structure has an additional DSP processor on chip. The YS-RDSP can execute maximum four instructions in parallel. To make program size shorter, 16-bit and 32-bit instruction lengths are supported in YS-RDSP. The YS-RDSP provides programmability. controllability, DSP processing ability, and includes eight-kilobyte on-chip ROM and eight-kilobyte RAM. System controller on the chip gives three power-down modes for low-power operation, and SLEEP instruction changes operation statue of CPU core and peripherals. YS-RDSP processor was implemented with Verilog HDL on top-down methodology, and it was improved and verified by cycle-based simulator written in C-language. The verified model was synthesized with 0.7um, 3.3V CMOS standard cell library, and the layout size was 10.7mm78.4mm which was implemented by using automatic P&R software.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.4A
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• pp.414-422
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• 2011

This paper describes a design of low-density parity-check(LDPC) decoder supporting block length 2,304-bit and code rate 1/2 of IEEE 802.16e mobile WiMAX standard. The designed LDPC decoder employs the min-sum algorithm and partially parallel layered-decoding architecture which processes a sub-matrix of $96{\times}96$ in parallel. By exploiting the properties of the min-sum algorithm, a new memory reduction technique is proposed, which reduces check node memory by 46% compared to conventional method. Functional verification results show that it has average bit-error-rate(BER) of $4.34{\times}10^{-5}$ for AWGN channel with Fb/No=2.1dB. Our LDPC decoder synthesized with a $0.18{\mu}m$ CMOS cell library has 174,181 gates and 52,992 bits memory, and the estimated throughput is about 417 Mbps at 100-MHz@l.8-V.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.9
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• pp.104-112
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• 2005

This paper presents the technique to develop an operational flight program(OFP) of avionic system computer(ASC) which integrates the avionics control, navigation and fire control and provides informations for flight, navigation and weapon aiming missions. For the development of the OFP of ASC, two i960KB chips are used as central processing units board and standard computer interface library(SCIL) which is built in house is used. The Irvine compiler corporation(ICC) integrated development environment(IDE) and the programming language Ada95 are used for the OFP development. We designed the OFP to a computer software configuration item(CSCI) which consists of to three parts for independency of software modules. The OFP has been verified through a series of flight tests. The relevant tests also have been rigorously conducted on the OFP such as software integrated test, and ground functional test.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.112-117
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• 2007

This paper presents specialized DSP instructions and their hardware architecture for audio coding algorithms, such as the MPEG-2/4 Advanced Audio Coding(AAC), Dolby AC-3, MPEG-2 Backward Compatible(BC), etc. The proposed architecture is specially designed and optimized for the MDCT/IMDCT(Inverse Modified Discrete Cosine Transform), and Huffman decoding of the AAC decoding algorithm. Performance comparisons show a significant improvement compared with TMS320C62x and ASDSP21060 for the MDCT/IMDCT computation. In addition, the dedicated Huffman decoding accelerator performs decoding and preparing operand in only one cycle. The proposed DPU(Data Processing Unit) consists of 107,860 gates and achieves 150 MIPS.