• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.818-821
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• 2010

본 논문에서는 차량 레이더 시스템용 시그마-델타 변조기를 제안한다. 개발된 변조기는 차량 레이더 시스템에서 고주파 대역 신호의 고해상도 데이터 변환, 즉 아날로그-디지털변환을 수행하는데 사용되며 저전압 및 저 왜곡 특성을 가진 몸체효과 보상형 스위치 구조로 구현되어 있다. 제안된 변조기는 0.25 마이크론 이중 폴리 3-금속 표준 CMOS 공정으로 제작되었고, $1.9{\times}1.5mm^2$의 다이 면적을 점유한다. 제안된 회로는 2.7V의 동작 전압에서 기존의 부트스트랩형 회로보다 약 20dB 향상된 우수한 총 고조파 왜곡 특성을 보였다.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• Proceedings of the KIEE Conference
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• 2007.10c
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• pp.163-165
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• 2007

본 연구는 무전극 형광램프의 램프 이상 유무를 검출하여 램프에 이상이 발생한 경우 이를 검출하여 전자식 안정기 회로를 보호하는 방법을 제안하고 실험을 통해 검증한다. 제안된 보호회로는 램프 양단에 걸리는 전압을 검출하여 디지털 회로에서 이용할 수 있는 신호로 변환해주는 아날로그 회로부와 이 신호를 이용해 안정기 회로의 인버터 부에 공급되는 PWM 신호를 제거해 주는 디지털 회로부로 구성된다. 제안된 알고리즘은 개발 비교기 IC 소자와 EPLD를 이용해 간단한 회로로 제작되었으며, 차후 집적화에도 유리할 것으로 판단된다.

• Journal of IKEEE
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• v.26 no.4
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• pp.577-583
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• 2022

Verilog-HDL-based modeling can be performed to confirm the fast operation characteristics after setting the design parameters of each block considering the stability of the system by performing linear phase-domain modeling on the phase-locked loop. This paper proposed Verilog-HDL modeling including DCO noise and DTC nonlinear characteristic. After completing the modeling, the time-domain transient simulation can be performed to check the feasibility and the functionality of the proposed PLL system, then the phase noise result from the system design based on the functional model can be verified comparing with the ideal phase noise graph. As a result of the comparison of simulation time (6 us), the Verilog-HDL-based modeling method (1.43 second) showed 484 times faster than the analog transistor level design (692 second) implemented by TSMC 0.18-㎛.

• The Journal of the Convergence on Culture Technology
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• v.6 no.3
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• pp.427-430
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• 2020

The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.27-34
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• 2002

There is much interest on information communications owing to the rapid development of network and IT(Information Technology). Analog signals are converted into digital signals for information communications. However, it is very difficult to completely erase the distortion induced during the conversion of analog signals such as voices and images into digital signals. Existing audio graphic equalizer requires very complex processes to calculate the gain and coefficients of the higher-order filter which is required to generate natural sound and to satisfy the need of each person. Unfortunately it is uneconomical and very difficult to embed the existing digital audio equalizer in the system because of the complexity of the existing digital audio equalizer for high quality sound. This paper discusses the design of a new digital audio graphic equalizer(DAGEQ) which can improve system performance and the quality of audio sound, and can be embedded in the system. This new DAGEQ is designed so that the gain can be controlled automatically. The automatic control of coefficients and gain empowers real time processing and the improvement of audio quality.

• The Journal of the Acoustical Society of Korea
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• v.21 no.7
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• pp.606-613
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• 2002

In this paper we applied a transmit beamforming technique to the underwater acoustic communication system for high rate data transmission. A prototype transmit system was designed and implemented with the general purpose DSP processor and multiple digital-to-analog converters. The performances of the implemented system were evaluated by the experiment in water tank. In order to simplify the procedure the channel coding and equalizer were omitted. And the simplest OOK (On-Off Keying) technique in digital communication methods was applied. The experimental result shows that the transmission data rate is higher about 3 times in the case of 5 hydrophone transmitting may than 1 hydrophone transmitter at bit error rate 10/sup -2/. We verified that the maximum data rate was 400 bps for speech signal transmission in water tank.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.1
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• pp.60-65
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• 2008

In this paper, we concern the stability of smart space by using the robust digital controller. The proposed methodologies are based on the intelligent digital redesign (IDR). More precisely, we represent the nonlinear and uncertain analog system as the Takaki-Sugeno (T-S) fuzzy model. Then the IDR problem can be reduced to find the digital gains minimizing the norm distance between the closed-loop states of the analog and digital control. Its constructive conditions are expressed as the linear matrix inequalities (LMIs). At last, a numerical example, HVAC system, is demonstrated to visualize the feasibility of the proposed methodology.

• Proceedings of the KAIS Fall Conference
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• 2005.05a
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• pp.169-172
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• 2005

반도체 기술의 발달과 더불어 디지털 신호 기억회로는 매우 빠른 속도로 발달되었다. 그러나 수 GHz 이상의 높은 고주파 신호를 저장하였다가 복재하는 것은 매우 어려운 기술이다. 고주파 신호의 복재를 위해서 과거에는 신호 감쇄가 적은 고주파 케이블을 일정한 길이로 감아서 시간지연을 시키는 아날로그 방식의 고주파 신호 저장회로가 사용되었으나, 신호 샘플링 및 광대역 신호 변환기 등이 발전되면서 고주파 신호를 고속으로 샘플링 한 뒤 디지털 회로에 저장 한 후에 필요시 고주파 신호를 복재하는 기술이 가능해 쳐다. 본 논문에서는 주파수 대역이 3 옥타브 이상 되는 광대역 고주파 신호를 저장하고 복재할 때 샘플링 주파수에 따른 특성을 분석하였다.