• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2008-2010
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• 2003

본 논문은 디지털 재설계 기법을 이용한 PWM 제어기 설계 기법을 제안한다. 디지털 재설계 기법은 잘설계된 아날로그 제어기의 성능을 보장하도록 변환하는 기법이다. 재설계된 디지털 제어기는 등가 영역의 법칙을 사용하여 PWM 제어기로 변환한다. 제안된 기법의 효용성을 검증하기 위하여 인공위성의 자세제어 시스템의 모의실험의 예를 보인다.

• Proceedings of the KSLP Conference
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• 1994.06a
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• pp.128-137
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• 1994

신호처리의 목적은 신호를 변형하여 우리가 원하는 형태로 만드는 것으로 신호를 변환시키는 장치 즉 시스템이 신호에 응답하여 다른 형태의 신호를 만들어 내는 것을 신호처리라 한다. 현재는 음성신호 처리시에 대부분 입력시호인 아날로그 신호(Analog Signal)를 표본화(Sampling)하고 양자화(Quantizing)하여 디지털 신호(Digital Signal)로 변환한 후 필요한 신호처리를 수행한다. 디지털 신호를 처리하므로써 정확성, 신뢰성, 처리속도를 증가시키게 되고 전자시스템(Electronic System)의 크기를 줄일 수가 있다. (중략)

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.162-168
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• 2005

In this paper, a digital current mode control is designed for the power converter applications. The designed digital current mode controller is derived analytically from the continuous time small signal model of the power converters. Due to the small signal model based derivations of the control law, the designed control method can be applicable to boost, buck, and buck-boost converters. It is also proven that the controlled power converter employing the designed digital current mode controller is always stable regardless of an operating conditions. In order to show the usefulness of a designed controller, experiments are carried out using a 16bit DSP micro-processor, TMS320LF2406A.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of the Korean Institute of Intelligent Systems
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• v.13 no.4
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• pp.397-402
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• 2003

This paper concerns a pulse-width-modulation (PWM) controller design technique using digital redesign. Digital redesign is to convert a well-designed analog controller into an equivalent pulse-amplitude-modulation (PAM) controller maintaining the original analog control system in the sense of state-matching. In similar line of conversion concept, the redesigned PAM controller is converted into a PWM controller using the equivalent area principle. To convincingly visualize the proposed technique, an computer simulation example-attitude control of artificial satellite system is included.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.503-506
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• 2001

There are four factors for patient monitoring : electrocardiography, blood pressure, temperature and respiration. While there are a lot of studies of E.C.C (electro-cardiography) monitoring system in the world, the studies of Respiratory system are not enough and leave much to be desired in the country. In this paper, we developed a respiratory system with the electrical impedance change of the lungs depending on the breath. Using the same electrode, we can monitor E.C.C and Respiration simultaneously, so we can monitor a patient's no-breathing state due to the central nerve paralysis in the emergency room easily. In this monitoring system, the analog part was made separated from the digital part for reducing power source noise and protecting patient from electric shock. The analog part consists of the several parts a high-frequency sine-wave generator, all amplifier for amplifying any impedance change signal, an analog processing part for rectifying and filtering. And the digital parts consists of three parts an AD convertor for converting analog signal to digital signal, digital filter, and a digital part for digital signal processing. This system's merits are using the same electrode with E.C.C and developing the multiple patient monitoring system easily.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.6
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• pp.726-731
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• 2004

This paper proposes a pulse-width-modulation (PWM) controller design technique using intelligent digital redesign. Intelligent digital redesign is to convert a well-designed analog fuzzy-model-based controller into an equivalent pulse-amplitude-modulation (PAM) digital controller maintaining the original analog control system in the sense of state-matching. In similar line of conversion concept, the redesigned PAM intelligent digital controller is converted into a PWM controller using the equivalent area principle. To convincingly visualize the proposed technique, an computer simulation example-attitude control of nonlinear artificial satellite system is included.

• Journal of the Korea Institute of Military Science and Technology
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• v.10 no.4
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• pp.132-137
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• 2007

The dynamic range of the radar which uses digital signal processors is limited by ADC(Analog-to-Digital Converter). That parameter and ADC loss depend on the noise level of radar receiver. In order to stabilize the performance of radar systems, it is necessary to maintain the noise level constantly. This paper presents the noise AGC(Automatic Gain Control) concept that can keep the noise level constantly and proves that the concept is acceptable through the hardware test and evaluation.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.