• Title/Summary/Keyword: 디지털 지연

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Pitch-shifted sound synthesis using digital waveguide model (피치 변화음의 합성을 위한 도파관 모델)

  • Cho, Sang-Jin;Kang, Myeong-Su;Chong, Ui-Pil
    • Journal of the Institute of Convergence Signal Processing
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    • v.10 no.2
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    • pp.127-131
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    • 2009
  • In the digital waveguide theory, traveling waves are represented by general solution to the wave equation that is second-order linear partial differential equation. The movement of these waves can be implemented using only delay lines. An unit delay in the general digital waveguide describes a sampling time interval. However, in the space-based digital waveguide the unit delay implies the spatial sampling distance. In consideration of these differences between two models, it is known that the space-based digital waveguide model is adequate to synthesize pitch-shifted sounds such as vibrato because the propagation distance can be directly control. In this paper, the time-based digital waveguide model which also synthesizes pitch-shifted sounds is proposed and compared with space-based digital waveguide.

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Improving the Accuracy of the Tapped Delay Time-to-Digital Converter Using Field Programmable Gate Array (Field-Programmable Gate Array를 사용한 탭 딜레이 방식 시간-디지털 변환기의 정밀도 향상에 관한 연구)

  • Jung, Do-Hwan;Lim, Hansang
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.9
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    • pp.182-189
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    • 2014
  • A tapped delay line time-to-digital converter (TDC) can be easily implemented using internal carry chains in a field-programmable gate array, and hence, its use is widespread. However, the tapped delay line TDC suffers from performance degradation because of differences in the delay times of dedicated carry chains. In this paper, a dual edge measurement method is proposed instead of a typical step signal to the delay cell to compensate for the performance degradation caused by wide-delay cells in carry chains. By applying a pulse of a fixed width as an input to the carry chains and using the time information between the up and down edges of the signal pulse, the timing accuracy can be increased. Two dedicated carry chain sites are required for the dual edge measurements. By adopting the proposed dual edge measurement method, the average delay widths of the two carry chains were improved by more than 35%, from 17.3 ps and 16.7 ps to 11.2 ps and 10.1 ps, respectively. In addition, the maximum delay times were improved from 41.4 ps and 42.1 ps to 20.1 ps and 20.8 ps, respectively.

포커스 e-기업-(주)우성포토교역

  • Park, Ji-Yeon
    • The Optical Journal
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    • s.96
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    • pp.34-35
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    • 2005
  • 코니카와 미놀타가 만나 탄생시킨 세계적인 디지털 이미징 전문회사 코니카 미놀타의 첫 번째 야심작인 DSLR ‘DYNAX 7D’발표회가 한국 에이전트인 (주)우성포토교역(대표·박노신) 주최로 지난 1월 25일 홀리데이인서울에서 열렸다. 합병 당시부터 세계적인 관심과 이목을 집중시킨 코니카미놀타는 금번 신제품 출 시를 기점으로 우성포토교역과 함께 한국의 디지털 사진시장에 새로운 도전과 변화를 예고하고 나섰다.

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디지털 카메라 시장 동향

  • Park, Ji-Yeon
    • The Optical Journal
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    • s.103
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    • pp.21-25
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    • 2006
  • 올해 국내 디카 성장률은 작게는 20%에서 30% 정도로 약 230만대 내외의 시장이 될 것으로 보인다. 올해 역시 식을 줄 모르는 디지털카메라의 인기 행진이 계속되면서 특히 지난해부터 본격화된 초창기 300만 화소 이하의 저화소대 디카를 구매했던 소비자들의 교체수요를 비롯한 시장 선점을 위한 메이커간의 경쟁이 그 어느 때보다 치열할 전망이다. 예전처럼 단순 화소 경쟁이 아닌 다양한 기능으로 차별화를 꾀하는 메이커들의 경쟁과 함께 국내 디카시장은 본격 성숙기에 들어설 것으로 보인다.

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Design of a 26ps, 8bit Gated-Ring Oscillator Time-to-Digital Converter using Vernier Delay Line (버니어 지연단을 이용한 26ps, 8비트 게이티드 링 오실레이터 시간-디지털 변환기의 설계)

  • Jin, Hyun-Bae;Park, Hyung-Min;Kim, Tae-Ho;Kang, Jin-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.2
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    • pp.7-13
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    • 2011
  • This paper presents a Time-to-Digital Converter which is a key block of an All-Digital Phase Locked Loop. In this work, a Vernier Delay Line is added in a conventional Gated Ring Oscillator, so it could get multi-phases and a high resolution. The Gated Ring Oscillator uses 7 unit delay cell, the Vernier Delay Line is used each delay cell. So proposed Time-to-Digital Converter uses total 21 phases. This Time-to-Digital Converter circuit is designed and laid out in $0.13{\mu}m$ 1P-6M CMOS technology. The proposed Time-to-Digital Converter achieves 26ps resolution, maximum input signal frequency is 100MHz and the digital output of proposed Time-to-Digital Converter are 8-bits. The proposed TDC detect 5ns phase difference between Start and Stop signal. A power consumption is 8.4~12.7mW depending on Enable signal width.

The blocking channel to reduce the performance decrease using the low correlation with cyclic delay scheme in LED-ID system (LED-ID 시스템에서 채널 차단에 따른 성능 열화를 줄이기 위한 저 상관 순환 지연 기법)

  • Lee, Kyu-Jin;Kim, Gui-Jung
    • Journal of Digital Convergence
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    • v.13 no.10
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    • pp.319-325
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    • 2015
  • We proposed the blocking channel to reduce the performance decrease using the low correlation with cyclic delay scheme in LED-ID system. LED-ID is based on the visible light to transmit the data. However, It is occurred the block channel by structure or environment of indoor for light of straightness. LED-ID system is degraded the performance by the block channel as loss of data, and burst error. To solve the block channel, the proposed system is overcome the burst error by low correlation among data, which is able to obtain the maximize time diversity gain to improve the performance of BER by cyclic delay scheme. The BER performance is evaluated by computer simulation according to channel parameter. The simulation results shows that proposed system gives much better performance than conventional system and constant cyclic delay scheme system.