• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.28-33
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• 2008

This paper presents a continuous-time equalizer adopting a clock loss tracking technique for digital display interface. This technique uses bottom hold circuit to detect the incoming clock loss. The generated loss signal is directly fed to equalizer filters, building adaptive feed-forward loops which contribute the stability of the system. The design was done in $0.18{\mu}m$ CMOS technology. Experimental results summarize that eye-width of minimum 0.7UI is achieved until -33dB channel loss at 1.65Gbps. The average power consumption of the equalizer is a maximum 10mW, a very low value in comparison to those of previous researches, and the effective area is $0.127mm^2$.

• Journal of IKEEE
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• v.22 no.3
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• pp.786-792
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• 2018

A third-order sigma-delta modulator with the architecture of cascade of integrator feedback (CIFB) is proposed for an analog-digital converter used in low-power sensor interfaces. It consists of three switched-capacitor integrators using a gain-enhanced current-mirror-based amplifier, a single-bit comparator, and a non-overlapped clock generator. The proposed sigma-delta analog modulator with over-sampling ratio of 160 and maximum SNR of 90.45 dB is implemented using $0.11-{\mu}m$ CMOS process with 1.2-V supply voltage. The area and power consumption of the sigma-delta analog modulator are $0.145mm^2$ and $341{\mu}W$, respectively.

• 한국HCI학회:학술대회논문집
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• 2006.02b
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• pp.197-202
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• 2006

본 연구에서는 휴대폰에서의 효과적인 사진 검색을 지원하기 위해 사진 정보를 이용한 검색 기능을 개발하고, 이의 사용성 평가 실험을 수행함으로써 개발된 검색기능의 효용성을 검증하였다. 본 연구에서 개발한 사진 검색 기능은 크게 날짜 검색기능과 키워드 검색 기능의 두 가지로 구분된다. 날짜 검색 기능은 입력한 날짜에 해당하는 사진이 포함된 화면을 사용자에게 제시하는 방식이며, 키워드 검색 기능은 사용자가 입력한 키워드가 포함된 파일 이름을 갖는 사진을 검색하여 그 결과를 제시하는 방식이다. 개발된 검색 방식과 기존의 사용자 조작에 따른 화면 네비게이션을 통한 검색 방식을 대상으로 사용성 평가 실험을 수행하였다. 또한, 휴대폰에 저장된 사진 장수에 따른 작업의 수행도 및 주관적 만족도를 비교 분석하기 위하여, 120, 240, 360 장의 사진을 저장하고 있는 프로토타입을 개발하여 사용성 평가 실험에 활용하였다. 사용성 평가 실험 결과, 사진 장수가 120, 240 장일 경우는 날짜 검색과 키워드 검색의 두 방식이 검색 편의성, 기능의 적합성, 전반적 만족도 등의 주관적 만족도 측면에서 기존 검색 방식에 비하여 우수한 사용성 수준을 갖는 것으로 분석되었다. 사진 장수가 360 장인 경우, 날짜 검색과 키워드 검색의 활용시 검색 편의성, 기능의 적합성, 전반적 만족도가 기존 검색 방식에 비하여 우수한 성능을 갖는 것으로 분석되었고, 특히, 키워드 검색을 활용한 경우 검색 시간이 기존 검색과 날짜 검색을 활용한 경우에 비하여 우수한 성능을 갖는 것으로 확인되었다. 본 연구는 화면 크기가 작고 입력 방식이 제한된 휴대폰 인터페이스 환경에서 효과적인 사진 검색방식을 제안하고 검증하였다는 데 의의를 가진다. 본 연구 결과는 휴대폰 메뉴 검색, 일반 파일 검색 뿐만아니라 디지털 카메라의 사진 관리 기능에도 응용될 수 있을 것으로 기대된다.

• Journal of Korea Game Society
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• v.12 no.2
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• pp.15-29
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• 2012

In order to predict satisfaction and performance of sensible healthcare game using motion recognition sensor, this study analyzed the effects of flow, presence and social cognitive factor and then, it attempted to verify structural relationships thereof. Self-efficacy, being a social cognitive factor, was found to affect the level of functional satisfaction of health game but it showed no direct effect to intention of using game. Flow experience was also observed to be a meaningful predictor for the level of functional and entertainment satisfaction in the direction hypothesized. It is also shown that presence exerts a direct effect on functional satisfaction. Finally, it is discovered that functional satisfaction has meaningful influence on entertainment satisfaction as well as future intention to use. The results verifies that even in sensible healthcare game, user experience and social cognitive factor have significant effects on satisfaction and performance of a serious game.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.129-132
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• 2003

In this paper, which sees the Strong-ARM SA1110 it used the main CPU and RTP in VoIP system. It will be able to apply the information communication field it embodied. It used the Tynux_box2 with the hardware side and it composed a VOIP system. And it used the RTP which is a real-time protocol in software control portion. The development environment of the paper that used the Target board and a Linux PC for connection used the RS-232C, USB connection, Ethernet LAN. The VoIP the environment for a communication used the wave file in the substitution which changes analog signal with the digital signal. And For the communication of the both sides it used the socket. This paper explained the fact that against a general technique from the operation of VoIP system. Using the Embedded linux development board which explained an operational process of the RTP protocol.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.1
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• pp.26-35
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• 2005

Generally, we employ FSMs for the design of controllers in digital systems. FSMs are Implemented with state diagrams generated from control flow. With HDL, we design and verify FSMs based on state diagrams. As the number of states in the system increases, the verification or modification processes become complicated, error prone and time consuming. In this paper, we propose a control flow oriented hardware description language at the register transfer level called Cycle-C. Cycle-C describes FSMs with timing information and control How intensive algorithms. The Cycle-C description is automatically converted into FSMs in the form of synthesizable RTL VHDL. In experiments, we design FSMs for control intensive interface circuits. There is little area difference between Cycle-C design and manual design. In addition, Cycle-C design needs only 10~50% of the number lines of manual RTL VHDL designs.

• Journal of KIISE:Information Networking
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• v.32 no.1
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• pp.110-122
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• 2005

Bluetooth has been reputed as a wireless networking technology supplying ad-hoc networks between digital devices. In particular, bluetooth scatternet is a most essential part for dynamic ad-hoc networks. But past researches on bluetooth scatternet has hardly treated dynamic scatternet environment. In this paper, we proposed a scatternet reformation algorithm for the case that some nodes escape from the scatternet. The proposed algorithm is a general algorithm which can be applied to many types of bluetooth scatternet regardless of the topology. The proposed algorithm has short reformation time delay because the process has only page process (not including inquiry process ). The algorithm is operated based on Recovery Node Vector which is composed of Recovery Master and Recovery Slave. In this paper, we performed the real hardware experiments for evaluating the performance of the proposed algorithm. In that experiments, we measured the reformation time and reformation probability. In comparison with the case including inquiry process, the proposed algorithm had the improvement in reformation time delay and we obtained high success rate over 97%.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.2
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• pp.187-195
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• 2000

Embedded software generates its outputs using current states of the system as well as external inputs. When a module in embedded software is tested, we need an automated testing tool, which generates possible sequences to reach the module as well as input data of the module, to reduce the testing time and to improve the quality of software. In this paper, we use decision table to specify the functionality of the module and data-annotated MSC (Message Sequence Charts) to describe scenarios, and implement a tool, which we call MSCTest, to automate the testing process. MSCTest consists of MSC graphic editor, test sequence and data generator, and test driver generator. MSCTest is effectively applied to test EsWin which is a kind of window library used in embedded systems.