• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39C no.1
• /
• pp.82-89
• /
• 2014

Recently, inertial sensors are popularly used for the location and position recognition of small devices for M2M/IoT. In this paper, we designed low power, low noise, small sized 6-axis inertial sensor IC for mobile applications, which uses a 3-axis piezo-electric gyroscope sensor and a 3-axis piezo-resistive accelerometer sensor. Proposed IC is composed of 3-axis gyroscope readout circuit, two gyroscope sensor driving circuits, 3-axis accelerometer readout circuit, 16bit sigma-delta ADC, digital filter and control circuit and memory. TSMC $0.18{\mu}m$ mixed signal CMOS process was used. Proposed IC reduces 27% of the current consumption of LSM330.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.2
• /
• pp.87-93
• /
• 2010

This paper presents a low-power, wide tuning range VCO with automatic two-step negative-Gm calibration loop to compensate for the process, voltage and temperature variation. To cover the wide tuning range, digital automatic negative-Gm tuning loop and analog automatic amplitude calibration loop are used. Adaptive body biasing (ABB) technique is also adopted to minimize the power consumption by lowering the threshold voltage of transistors in the negative-Gm core. The power consumption is 2 mA to 6mA from a 1.2 V supply. The VCO tuning range is 2.65 GHz, from 2.35 GHz to 5 GHz. And the phase noise is -117 dBc/Hz at the 1 MHz offset when the center frequency is 3.2 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.2
• /
• pp.61-66
• /
• 2011

A new via structure on printed circuit board has been proposed for differential signaling in applications of high-speed interconnection. In new structure, the via is physically separated and then divided into two electrically-isolated sections using mechanical drill routing process. These cutted vias are connected respectively to the traces of the differential pair. New via structure makes possible to rout the differential pair using only one via, while conventional via structure needs two vias for interconnection. Because the spacing even in via region keeps almost constant, new via structure can alleviate an impedance discontinuity and then enhance its signal transmission characteristics such as reflection loss and insertion loss. It is expected that new via structure is effective in differential signaling for high-speed interconnection.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.10
• /
• pp.1-6
• /
• 2007

Wireless Self-Powered Temperature Sensor for UHF Sensor Tags which are basic device for construction of ubiquitous sensor network is proposed. The key parameters of the target specification are resolution of $0.1\;^{\circ}C$ per output bit, below 1.5 V of operating voltage and below 5 uW of power consumption during sensing operation. Temperature sensor circuit consists of PTAT current generator, band gap reference circuit generating both reference voltage and current, Sigma-Delta Converter, and Digital Counter. Simulated maximum resolution was $0.23\;^{\circ}C/bit$ in 11-bit output. The proposed temperature sensor was fabricated by using a 0.25 m CMOS process. The chip area is $0.32\;{\times}\;0.22\;mm$ and the operating frequency is 2 MHz. Measured resolution from fabricated temperature sensor was $4\;^{\circ}C/bit$ in 8-bit output for the temperature range from $10^{\circ}C$ to $80^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.3
• /
• pp.44-53
• /
• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Journal of IKEEE
• /
• v.19 no.4
• /
• pp.535-540
• /
• 2015

A microstrip gas chamber (MSGC), applied to digital radiography system, was designed and constructed. The microstrip electrodes were fabricated with Chrome(Cr.). by photolithography process on Silicon(Si) wafer and glass substrate. The width of anode and cathode electrodes was $10{\mu}m$, and $290{\mu}m$, respectively. The distance of the electrodes was $100{\mu}m$, and the active area was $50{\times}50mm^2$. And the number of anode was 80. The microstrip electrodes were damaged when discharges occurred over the 600 V of anode voltage. As the result of experiments. It detected the typical output signals of the pulse width, 20 ns, under the condition that the detecting gas was Ar(90%) + $CH_4$(10%), X-ray tube voltage was 42 kV, and tube current was 1 mA.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.40 no.1
• /
• pp.9-15
• /
• 2015

A CMOS band-pass delta-sigma modulator(BPDSM) and cascode class-E power amplifier have been developed CMOS for Class-S power amplifier applications. The BPDSM is operating at 1-GHz sampling frequency, which converts a 250-MHz sinusoidal signal to a pulse-width modulated digital signal without the quantization noise. The BPDSM shows a 25-dB SQNR(Signal to Quantization Noise Ratio) and consumes a power of 24 mW at an 1.2-V supply voltage. The class-E power amplifier exhibits an 18.1 dBm of the maximum output power with a 25% drain efficiency at a 3.3-V supply voltage. The BPDSM and class-E PA were fabricated in the Dongbu's 110-nm CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.5C
• /
• pp.395-402
• /
• 2008

In this paper, an I/Q channel 12bits 40MS/s Pipeline Analog to Digital Converter that is able to apply to WLAN/WMAN system is proposed. The proposed ADC integrates DLL based duty-correction circuit which corrects the fluctuations in the duksty cycle caused by miniaturization of CMOS devices and faster operating speeds. It is designed as a 1% to 99% input clock duty cycle could be corrected to 50% output duty cycle. The prototype ADC is implemented in a $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process and dissipates 184mW at 1.8V single supply The SNDR of the proposed 12bit ADC is 52dB and SFDR of 59dBc(@Fs=20MHz, Fin=1MHz) is measured.

• Journal of the Korean Institute of Intelligent Systems
• /
• v.14 no.3
• /
• pp.285-289
• /
• 2004

Recently, due to the high development of the internet, needs for multimedia streams such as digital audio and video is increasing much more. In case of transmitting multimedia streams using the User Datagram Protocol (UDP), it may cause starvation of TCP traffic on the same transmission path, thus resulting in congestion collapse and enormous delay because UDP does not perform TCP-like congestion control. Because of this problem, diverse researches are being conducted on new transmission schemes and protocols intended to efficiently reduce the transmission delay of real-time multimedia streams and perform congestion control. The TCP-friendly congestion control schemes can be classified into the window-based congestion control, which uses the general congestion window management function, and the rate-based congestion control, which dynamically adjusts transmission rate by using TCP modeling equations and the like. In this paper, we suggest the square-root congestion avoidance algorithm with the hybrid TCP-friendly congestion control scheme which the window-based and rate-based congestion controls are dealt with in a combined way. We apply the proposed algorithm to the existing TEAR. We simulate the performance of the proposed TEAR by using NS, and the result shows that it gives better improvement in the stability needed for providing congestion control than the existing TEAR.

• Journal of the Korean Graphic Arts Communication Society
• /
• v.26 no.2
• /
• pp.65-77
• /
• 2008

The color reproduction of digital still camera does not, in general, match those of the final prints. Because color gamut of these devices is different, it is therefore necessary to take account of a way to match. The way uses the optimized profile to print an image. This paper proposed a way to create the input profile of digital still camera for standardization printing process. The results of proposed way showed that for input profiles equivalent, good results relatively. In this paper, an experiment was done where the illumination sources used as the standard illumination 5200K and illuminated at a $45^{\circ}$ angle in the best illumination efficiently. The white balance was in mode 'custom': aperture F11, exposure time 1/60s, ISO50, focal length 80mm. The images were exported and saved as 16bit RGB tiff(AdobeRGB, sRGB, ProphotoRGB) images. To do the test, the RGB values of the RGB tiff images are processed through the ICC input profile to arrive at processed $CIEL^*a^*b^*$ values. A profiling tool such as ProfileMaker 5.0 and Monacoprofile 4.8 are used to do this. The processed CIEL*a*b* values are compared to the reference CIEL*a*b* values and these two values are used to calculate a ${\Delta}E$.