• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.3
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• pp.497-502
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• 2018

An analog to digital converter(: ADC) has been designed to extract video signals of marine X-band radar and convert to digital signals in order to produce rainfall information. X-band weather radars are suitable for high temporal-spatial resolution observations of rainfall over local ranges but they are very expensive and require professional management. The marine radars with 10-2 cost facilitate data collection and management as well as economic benefits. To validate the usefulness of the developed ADC, comparative observations were made with weather radar for short term precipitation cases. The rainfall distribution of marine radar observations are consistent with that of weather radar within a radius of 15 km. This demonstrates the usability of marine radar for rainfall observations.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.42 no.7
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• pp.594-600
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• 2014

In modern warfare, securing communication channel by combatting opponents' electromagnetic attack is a crucial factor to win the war. Military satellite digital transponder is a communication payload of the next generation military satellite that maintains warfare networks operational in the presence of interfering signals by securely relaying signals between ground terminals. The transponder in this paper is classified as a partial processing transponder which performs cost effective secure relaying in satellite communication links. The control functions of transmission security achieve immunity to hostile interferences which may cause malicious effects on the link. In this paper, we present an efficient architecture for implementing the control mechanism. Two major ideas of pipelined processing in per-group control and software processing of blocked band information dramatically reduce the complexity of the hardware. A control code sequence showing its randomness with uniform distribution is exemplified and qualification test results are briefly presented.

• Journal of IKEEE
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• v.27 no.3
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• pp.273-279
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• 2023

The use of line memory is essential for image filtering in image processing hardware. After input data is stored in line memory, filtering is performed after synchronization to use the stored data. A sync generator is used for synchronization, and in the case of a conventional sync generator, the input sync signal is delayed by one row of the input image. If a signal delayed by two rows is required, it is necessary to connect two modules. This approach increases the size of the hardware and cannot be designed efficiently. In this paper, we propose a sync generator that generates multiple types of delayed signals by adding a finite state machine. The hardware design was coded in Verilog HDL, and performance is verified by applying it to image processing hardware using field programmable gate array board.

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• Journal of IKEEE
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• v.2 no.1 s.2
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• pp.1-14
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• 1998

In this paper, Antenna, LNA, Mixer, VCO, and Modulation/Demodulation in Baseband processor which are the RF main components in Wireless LAN system for ultra high-speed communications network are studied. Antenna bandwidth and selective fading due to multipath can be major obstacles in high speed digital communications. To solve this problem, wide band MSA which has loop-structure magnetic antenna characteristics is designed. Distributed mixer using dual-gate GaAs MESFET can achieve over 10dB LO/RF isolation without hybrid, and minimize circuit size. As linear mixing signal is produced, distortions can be decreased at baseband signals. Conversion gain is achieved by mixing and amplification simultaneously. Mixer is designed to have wide band characteristics using distributed amplifier. In VCO design, Oscillator design method by large signal analysis is used to produce stable signal. Modulation/Demodulation system in baseband processor, DS/SS technique which is robust against noise and interference is used to eliminate the effect of multipath propagation. DQPSK modulation technique with M-sequences for wideband PN spreading signals is adopted because of BER characteristic and high speed digital signal transmission.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.3
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• pp.93-101
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• 2001

In this paper, we propose an image downscaler used in multimedia video applications, such as DTV, TV-PIP, PC-video, camcorder, videophone and so on. The proposed image downscaler provides a scaled image of high-quality and high-performance. This paper will explain the scaling theory using two-dimensional digital filters. It is the method that removes an aliasing noise and decreases the hardware complexity, compared with Pixel-drop and Upsamling. Also, this paper will prove it improves scaling precisians and decreases the loss of data, compared with the Scaler32, the Bt829 of Brooktree, and the SAA7114H of Philips. The proposed downscaler consists of the following four blocks: line memory, vertical scaler, horizontal scaler, and FIFO memory. In order to reduce the hardware complexity, the using digital filters are implemented by the multiplexer-adder type scheme and their all the coefficients can be simply implemented by using shifters and adders. It also decreases the loss of high frequency data because it provides the wider BW of 6MHz as adding the compensation filter. The proposed downscaler is modeled by using the Verilog-HDL and the model is verified by using the Cadence simulator. After the verification is done, the model is synthesized into gates by using the Synopsys. The synthesized downscaler is Placed and routed by the Mentor with the IDEC-C632 0.65${\mu}{\textrm}{m}$ library for further IC implementation. The IC master is fixed in size by 4,500${\mu}{\textrm}{m}$$\times$4,500${\mu}{\textrm}{m}$. The active layout size of the proposed downscaler is 2,528${\mu}{\textrm}{m}$$\times$3,237${\mu}{\textrm}{m}$.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.4
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• pp.695-704
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• 2018

The rainfall cases were identified by rainfall estimation techniques which were developed by using X - band marine radar. A digital signal converter was used to convert the signal received from the marine radar into digital reflectivity information. The ground clutter signal was removed and the errors caused by beam attenuation and beam volume changes were corrected. The reflectivity showed a linear relationship with the rain gauge rainfall. Quantitative rainfall was estimated by converting the radar signal into an cartesian coordinate system. When the rainfall was recorded more than $5mm\;hr^{-1}$ at three automatic weather stations, the rain cell distribution on the marine radar was consistent with that of the weather radar operated by Korea meteorological Adminstration.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8A
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• pp.1252-1258
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• 1999

This paper describes a COMS IF transceiver IC for 10-MHz bandwidth wireless local loops. It interfaces between the RF section and the digital MODEM section and performs the IF-to-baseband (Rx) and baseband-to-IF (Tx) frequency conversions. The chip incorporates variable gain amplifiers, phase-locked loops, low pass filters, analog-to-digital and digital-to-analog converters. It has been implemented in a 0.6 -${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS process. The phase-locked loops include voltage-controlled oscillators, dividers, phase detectors, and charge pumps on chip. The only external complonents are the filter and the varactor-tuned LC tank circuit. The chip size is 4 mm $\times$ 4 mm and the total supply current is about 57 mA at 3.3 V.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.26 no.1
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• pp.101-108
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• 1990

The processing efficiency of the special purpose hardware which is designed and implemented for the FFT caculation was investigated in this paper. This hardware equipment was consisted of LSI chips of four high speed multiplier and adde $r_stractor, and was interfaced with the 16bit microcomputer(NEC PC-9801E). The FFT processing time by this hardware equipment was improved approximately 4.8 times by the co-processor(Intel C8087-3).3).

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.89-92
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• 2001

In this paper, as a study of programmable software radio digital communication, we implemented ASK(Amplitude Shift Keying), FSK(Frequency Shift Keying), and PSK(Phase Shift Keying) modulation using programmable software(algorithm) of DSP(Digital Signal Processor). Moreover, it is possible to select one of those three modulation methods by realizing on single DSP. We adopted Motorola DSP56002 and Crystal CS4215(A/D and D/A converter) for our purpose. The DSP56002 is 24-bit and operates 20 MIPS at 40 MHz, and the CS4215 is 16-bit and supports the maximum 50 kHz sampling frequency.