• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.5
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• pp.35-41
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• 2008

This paper presents the design method of current-mode signal processing for high speed and low power digital audio signal processing. The digital audio processor requires a digital signal processing such as fast Fourier transform (FFT), which has a problem of large power consumption according to the settled point number and high speed operation. Therefore, a current-mode signal processing with a switched Current (SI) circuit was employed to the digital audio signal processing because a limited battery life should be considered for a low power operation. However, current memory that construct a SI circuit has a problem called clock-feedthrough. In this paper, we examine the connection of dummy MOS that is the common solution of clock-feedthrough and are willing to calculate the relation of width between dummy MOS for a proposal of the design methodology for improvement of current memory. As a result of simulation, in case of that the width of memory MOS is 20um, ratio of input current and bias current is 0.3, the relation of width between switch MOS and dummy MOS is $W_{M4}=1.95W_{M3}+1.2$ for the width of switch MOS is 2~5um, it is $W_{M4}=0.92W_{M3}+6.3$ for the width of switch MOS is 5~10um. Then the defined relation of MOS transistors can be a useful design guidance for a high speed low power digital audio processor.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.947-950
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• 2000

디지털 데이터 처리 및 전송과 함께 방대한 양의 디지털 데이터에 대한 저장 시스템의 용량 증가를 위한 신호처리 기법에 대해 관심이 날로 증가하고 있는 가운데, 다양한 기록 시스템에 대하여 고안된 여러 가지 채널 코딩 및 신호 검출 알고리즘을 분석, 검증하기 위한 시뮬레이터를 하드웨어적으로 구현하였다. 본 시뮬레이터는 광 기록 저장 채널에 대한 신호처리 시뮬레이션프로그램을 토대로 디지털 신호처리 프로세서(DSP)를 이용하여 RLL 변조 코드에 대한 인코더/디코더 및 채널을 통과한 데이터에 대해 심볼간 간섭을 제거하기 위한 등화기와 등화된 채널 출력 신호로부터 전송된 데이터를 결정하기 위한 여러 가지 신호 검출기를 설계하여 채널을 통과하기 전의 원본 데이터와 통과후의 출력 값에 대한 에러율을 분석, 검증하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.6 no.2
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• pp.38-46
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• 2001

This paper presents a new multiprocessor system and corresponding scheduling algorithm that can be applied for implementation of fine grain DSP algorithms such as digital filters. The newly proposed system uses one or more shared buses as the basic interconnection network between processors, and fixed amount of clock-skew is maintained between instruction execution of processors. This system not only can handle the interprocessor communications very efficiently but also can explicitly incorporate the interprocessor communication delay time into the multiprocessor scheduling model. This paper also presents a new scheduling strategy for implementing digital filters expressed in fully-specified flow graphs on the proposed system. The simulation result shows that well-known digital filters can be implemented on proposed multiprocessor in which the implementation satisfies the iteration period bound.

• Proceedings of the Acoustical Society of Korea Conference
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• autumn
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• pp.249-252
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• 2004

본 논문에서는 TeakLite DSP 프로세서를 이용하여 캠코더에서 레코딩을 할 때 모터 소음과 주변 잡음이 입력되어 오디오 신호의 명료도가 떨어지는 문제점을 해결하기 위한 잡음 제거 기법의 실시간 구현에 대해서 기술하고자 한다. 잡음 제거를 위해서는 일반적으로 많이 사용되고 있는 Spectral Subtraction 기법을 사용하였다. 알고리즘 구현시 MIPS 감소에 효과적이었던 최적화 기법들을 적용하여 TeakLite DSP 프로세서에서 최적화되어 동작하도록 하였다. 최적화된 Spectral Subtraction 어셈블리 코드는 TeakLite DSP 프로세서에서 32 kHz, 16 bit 입력에 대해 40 MIPS에서 동작하였다.

• The Journal of the Acoustical Society of Korea
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• v.18 no.1
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• pp.3-9
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• 1999

This paper concerns performance of a parallel digital signal processing system. The performance of the system is analyzed in terms of CPU cycles required for 1024-point FFT computation. The number of cycles is estimated in three different approaches; FFT algorithm-based, assembly level source code-based, and probability-based. The results of analysis indicate that on a bus-based system the best performance for FFT is achieved with a single board. Because in some applications like FFT, where frequent data exchanges among processors occur, the number of communication cycles increases as the number of boards. It is observed that inter-board communication degrades overall system performance for the FFT computation. Also shown is that linear increase in performance can be obtained if multiple buses are employed.

• The Journal of the Acoustical Society of Korea
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• v.4 no.1
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• pp.22-34
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• 1985

소나 신호 처리에서, 흔히 발생하는 난반사에 의한 잡음 때문에, 기존에 사용되어지고 있는 앨고 리즘으로 처리하기에는 많은 문제점을 내포하고 있다. 본 연구는 소나 시스템의 신호 처리를 위하여 마 이크로 프로세서를 사용하였으며, 신호처리 방법은 코릴레이숀 접음과 반사음을 식별하고, 거기서 평가 된 것을 기준으로 직접음만의 신호를 재생하여 반사음을 처리하였다. 실험의 결과치와 계산치를 비교한 결과, 무향 수조의 특성에 의한 오차를 제외하고는 거의 오차가 없었으며, 그 오차는 주파수가 낮아짐에 따라 증가하였다. 실험 결과를 토대로 처리 시스템의 소형·단순화가 가능한 것으로 분석되었다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.36-42
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• 2007

In this paper, we have studied temperature compensation architecture for a bust mode optical transmitter to convert the electric burst mode date signal to a optical one through the laser diode. In order to get stable high speed data transmission, we used digital sampling technique with a microprocessor for the temperature compensation of the laser diode, not the previous real time analog technique. Though the digital automatic power control circuit should be complemented the previous analog one with accuracy and effectiveness. So the digital technique will be more effective in further future in development for the over Gb/s transmitting speed.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.941-944
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• 2012

Microprocessor is widely used in various industries. So it is very important to learn about it. But it is very difficult because students must know about both hardware and software of it. Student usually learn about it with a complete educational product in many technical high school. It make them to have no chance to mixed various electronic parts such as sensors, motors and so on. It cause them to low the creative product making ability. So we adjust new course with the arduino instead of the complete educational product to microprocessor education. It help student to high the electronic part mixing ability and the creative electronic product making ability.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1776-1782
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• 2010

The interferometric fiber optic gyroscopes (FOGs) are well known as sensors of rotation, which are based on Sagnac effect, and have been under development for a number of years to meet a wide range of performance requirements. This paper describes the development of open-loop FOG and digital signal processing techniques implemented on FPGA. Our primary goal was to obtain intermediate accuracy (pointing grade) with a good bias stability (0.22deg) and scale factor stability, extremely low angle random walk (0.07deg) and significant cost savings by using a single mode fiber. A secondary goal is to design all digital FOG signal processing algorithms with which the SNR at the digital demodulator output is enhanced substantially due to processing gain. The Cascaded integrator bomb(CIC) type of decimation filter only requires adders and shift registers, low cost processors which has low computing power still can used in this all digital FOG processor.

• The Magazine of the IEIE
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• v.7 no.2
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• pp.13-26
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• 1980

지난 20년 동안 디지털(digital) 통신은 괄목할 만한 발전을 해 왔다. 이는 컴퓨터, 집적회로, 디지털 신호처리 기술의 급격한 발전으로부터 직접적으로 크게 영향을 받았기 때문이다. 디지털 통신은 잡음, 타신호와의 간섭, 비선형 증폭기 사용에 의한 성능 저하 등의 어네로그(analog) 통신에서의 문제점들을 해결하고, 또한 대형집적회로 또는 마이크로프로세서를 사용함으로써의 이점, 즉 time sharing, 기기 유지관리의 용이성, 경제적인 점 등 여러 가지 장점이 있기 때문에 앞으로 그 발전은 가속화되어 결국 어네로그 통신과 대체될 전망이다. 여기에서는 현재 디지털 통신의 주종이 되고 있는 PCM을 중심으로 한 통신시스템(PCM 부호화, 교환, 다종화, 회로구성)을 설명하고 비교적 새로운 분야인 컴퓨터통신, 인공위성통신, 광통신, 디지털 통신에서의 대역폭 축소와 channel capacity를 증가시키는 방법들을 토의함으로써 디지털 통신기술의 현황과 앞으로의 전망에 관하여 검토하였다.