• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.6
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• pp.1413-1421
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• 2014

This paper realize power control embedded system with one master of Core-A 32-bit RISC processor and several slaves controling power with synchronized digital signals. Core-A platform is consisted of Core-A processor, AMBA bus, SSRAM, AC97, DMA, UART, GPIO etc. Slave is made by both digital part and analog part. The former generates various power control patterns synchronized with master signal. The latter converts 220V power proportional to 4 bit digital signals. design of Embedded system is executed in Flowrian II, in which software is cross-compiled and hardware is verified by simulation. Embedded system is implemented in FPGA board and CPLD chips as well as PCB board for analog power control.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.6
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• pp.77-88
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• 2008

This paper addresses the implementation of FTTH system based on G-PON technology. This system supports the duplication function that can switchover both TDM and data routes within 10msec. This system consists of OLT and ONU/ONT. G-PON OLT supports the maximum 32 2.5Gbps interfaces, and then has the flexibility and the scalability for supplying digital communication and broadcasting convergence service in the near future. OLT system consists switch module, subscriber module, processor module, and G-PON link module, and has the operating system based on Linux. ONU is installed in customer premise to supply TPS (Triple Play Service). Also ONT has the dedicated interface for IP-TV to improve the transmission characteristics of IP-TV signal.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.1
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• pp.63-68
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• 2011

Many countries all over the world have been doing lunar exploration projects. Korea has also been doing basic research on lunar exploration. The development of communication systems for lunar exploration projects is one of the most important aspects of performing a successful lunar mission. In this paper, we design a DSP (Digital Signal Processor) prototype based on the requirement analysis of a communication link for lunar exploration and implement its core module considering the international standards for deep space communications to perform a basic research on baseband processor development. It is verified by comparing the bit error rate of the DSP prototype with that of a computer simulation.

• The Journal of Information Technology
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• v.7 no.2
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• pp.19-28
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• 2004

Many kind of operators using Residue Number System are used to design the special purpose processor for many merits in Digital Signal Processing, Computer Graphics, etc. But It get demerits for general division and the magnitude comparison. In this paper, general division operator for divisor with a small number in RNS is proposed. If the result of division using the multiplicative inverse has remainder, the quotient of this is larger than maximum quotient of division that has the same divisor to dividend of the maximum size. This condition is used for the ending condition of the recursive operation. And, the divisor is substitute for the compared value of quotients. So, the proposed division operator has a small size and fine operation speed, but with the limitation of divisor.

• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.487-501
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• 2007

To achieve high resource utilization for multi-issue DSPs, production compiler commonly includes variants of iterative modulo scheduling algorithm. However, excessive cyclic data dependences, which exist in communication and media processing loops, unduly restrict modulo scheduling freedom. As a result, replicated functional units in multi-issue DSPs are often under-utilized. To address this resource under-utilization problem, our paper describes a novel compiler preprocessing strategy for effective modulo scheduling. The preprocessing strategy proposed capitalizes on two new transformations, which are referred to as cloning and dismantling. Our preprocessing strategy has been validated by an implementation for StarCore SC140 DSP compiler.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.14 no.5
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• pp.41-48
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• 2005

The Rotating transmission is made up of belts, mass disks and gears. This transmission is controlled electro-mechanically by the motor and operation program. The control strategy of the system can be to change belts' stiffness and the masses of mass disk and gear. This system can be modeled as a rigid body, and also finds broad application in such diverse fields as machine tools, the cruise control system In automobiles, and control in the attitude and gimbals of spacecraft. This Transmission proves the necessity and effect of a closed loop control. The study of the Rotating Transmission excited by its base motion is able not only to predict the rotational performance, but to obtain the fundamental data for vibration isolation. In this research, we compared the response characteristics of the two controllers by means of the experiments on PD controller and PID controller added on integral action. Furthermore, we studied the response abilities such as steady state error, overshoot, and ect. and the response velocities such as rising time, settling time, and ect. in the rotating transmission.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Journal of Broadcast Engineering
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• v.19 no.6
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• pp.819-825
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• 2014

In this paper, monaural ambient component extraction algorithm based on nonnegative matrix factorization (NMF) is described. The ambience component extraction algorithm in this paper is developed for audio upmixing system; Recent researches have shown that they can enhance listener envelopment if the extracted ambient signal is applied into the multichannel audio upmixing system. However, the conventional method stores all of the audio signal and processes all at once, so it cannot be applied to streaming system and digital signal processor (DSP) system. In this paper, the ambient component extraction algorithm based on on-line nonnegative matrix factorization is developed and evaluated to solve the problem. As a result of analysis of the processed signal with spectral flatness measures in the experiment, it was shown that the developed system can extract the ambient signal similarly with the conventional batch process system.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.5
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• pp.12-19
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• 2007

This paper presents an ASIP(Application Specific Instruction Set Processor) for implementation of H.264/AVC, called VSIP(Video Specific Instruction-set Processor). The proposed VSIP has novel instructions and optimized hardware architectures for specific applications, such as intra prediction, in-loop deblocking filter, integer transform, etc. Moreover, VSIP has hardware accelerators for computation intensive parts in video signal processing, such as inter prediction and entropy coding. The VSIP has much smaller area and can dramatically reduce the number of memory access compared with commercial DSP chips, which result in low power consumption. The proposed VSIP can efficiently perform in real-time video processing and it can support various profiles and standards.

• Journal of IKEEE
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• v.14 no.3
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• pp.190-198
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• 2010

This paper describes a auto focus piezo actuator driver IC for portable digital camera. The 80[V] DC voltage is generated by a DC-DC converter and supplied to power of piezo moving control circuit. The voltage of piezo actuator needs range -20[V] to 80[V] proportional to 1[Vp-p] input control voltages. The dimensions and number of external parts are minimized in order to get a smaller hardware size. IIC(Inter-IC) interface logic is designed for data interface and it makes debugging easy, test for mass productions. The power consumption is around 40[mW] with supply voltage of 3.6[V]. This device has been fabricated in a 0.6[um] double poly, triple metal 100[V] BCD MOS process and whole chip size is 1600*1500 [$um^2$].