• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.11
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• pp.779-789
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• 2014

Cognitive radio (CR) technology based on geo-location database access approach and/or wideband spectrum sensing approach is absolutely vital in order to recognize available frequency bands in white spaces (WSs), and efficiently utilize shared spectrums. This paper presents a new structure for the TVWS database access protocol implementation based on Internet Engineering Task Force (IETF) Protocol to Access WS database (PAWS). A wideband compressive spectrum sensing (WCSS) scheme using a modulated wideband converter is also proposed for the TVWS utilization. The developed database access protocol technology which is adopted in both the TV band device (TVBD) and the TVWS database operates well in the TV frequency bands. The proposed WCSS shows a stable performance in false alarm probability irrespective of noise variance estimation error as well as provides signal detection probabilities greater than 95%. This paper also investigates Federal Communications Commision (FCC) regulatory requirements of TVWS database as well as European Telecommunications Standards Institute (ETSI) policy related to TVWS database. A standardized protocol to achieve interoperability among multiple TVBDs and TVWS databases, which is currently prepared in the IETF, is discussed.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1193-1203
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• 2008

An active antenna(AA) can have wider bandwidth and more gain with small antenna size than those of passive antennas. However, AA inherently generates thermal noise and spurious signals from an active device. Moreover, the spurious performance of AA is very important in a highly sensitive receiving system since it is located at the front end of the receiving system. In this study, we developed an AA with $100{\sim}500\;MHz$, having the output P1dB higher than 3 dBm and little spurious signals in real environments. To achieve such performance, we designed an AA with 3-stage amplifier using CD(common drain) FET and 2 BJTs. Its electrical performances were simulated using ADS. The measurement results for typical gain, NF, OIP3, VSWR and P1dB in the required frequency band were 9.7 dBi, 10 dB, 14 dBm, 1.7:1 and 3 dBm respectively. They are in good agreement with simulation results. The unwanted spectrum level of the proposed AA is $10{\sim}30\;dB$ lower than that of the antenna with CS(common source) FET configuration at a west suburban area of Seoul, which shows that the proposed AA can be applicable to a highly sensitive receiving system for detecting unknown weak signals mixed with broadcasting and civilian communication signals.

• Journal of Korea Game Society
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• v.12 no.5
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• pp.79-88
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• 2012

In this paper, we present a real-time hand pose recognition method to provide an intuitive user interface through hand poses or movements without a keyboard and a mouse. For this, the areas of right and left hands are segmented from the depth camera image, and noise removal is performed. Then, the rotation angle and the centroid point of each hand area are calculated. Subsequently, a circle is expanded at regular intervals from a centroid point of the hand to detect joint points and end points of the finger by obtaining the midway points of the hand boundary crossing. Lastly, the matching between the hand information calculated previously and the hand model of previous frame is performed, and the hand model is recognized to update the hand model for the next frame. This method enables users to predict the hidden fingers through the hand model information of the previous frame using temporal coherence in consecutive frames. As a result of the experiment on various hand poses with the hidden fingers using both hands, the accuracy showed over 95% and the performance indicated over 32 fps. The proposed method can be used as a contactless input interface in presentation, advertisement, education, and game applications.

• Journal of the Korean Vacuum Society
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• v.20 no.1
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• pp.22-29
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• 2011

An infrared thermographic imaging module of [$320{\times}256$] focal-plane array (FPA) based on [InAs/GaSb] strained-layer superlattice (SLS) was fabricated, and its images were demonstrated. The p-i-n device consisted of an active layer (i) of 300-period [13/7]-ML [InAs/GaSb]-SLS and a pair of p/n-electrodes of (60/115)-period [InAs:(Be/Si)/GaSb]-SLS. FTIR photoresponse spectra taken from a test device revealed that the peak wavelength (${\lambda}_p$) and the cutoff wavelength (${\lambda}_{co}$) were approximately $3.1/2.7{\mu}m$ and $3.8{\mu}m$, respectively, and it was confirmed that the device was operated up to a temperature of 180 K. The $30/24-{\mu}m$ design rule was applied to single pixel pitch/mesa, and a standard photolithography was introduced for [$320{\times}256$]-FPA fabrication. An FPA-ROIC thermographic module was accomplished by using a $18/10-{\mu}m$ In-bump/UBM process and a flip-chip bonding technique, and the thermographic image was demonstrated by utilizing a mid-infrared camera and an image processor.

• The Journal of the Korea Contents Association
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• v.15 no.9
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• pp.21-28
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• 2015

In the semi-conductor process, a simulation process is performed to detect defects by analyzing the behavior of the impurity through the physical quantity calculation of the inner element. In order to perform the simulation, Finite-Difference Time-Domain(FDTD) algorithm is used. The improvement of semiconductor which is composed of nanoscale elements, the size of simulation is getting bigger. Problems that a processor such as CPU or GPU cannot perform the simulation due to the massive size of matrix or a computer consist of multiple processors cannot handle a massive FDTD may come up. For those problems, studies are performed with parallel/distributed computing. However, in the past, only single type of processor was used. In GPU's case, it performs fast, but at the same time, it has limited memory. On the other hand, in CPU, it performs slower than that of GPU. To solve the problem, we implemented a computing model that can handle any FDTD simulation regardless of size on the cluster which consist of heterogeneous processors. We tested the simulation on processors using MPI libraries which is based on 'point to point' communication and verified that it operates correctly regardless of the number of node and type. Also, we analyzed the performance by measuring the total execution time and specific time for the simulation on each test.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2251-2259
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• 2009

We propose an algorithm and system which generates 3D stereo image by composition of 2D image from 4 multiple clusters which 1 cluster was composed of 4 multiple cameras based on network. Proposed Schemes have a network-based client-server architecture for load balancing of system caused to process a large amounts of data with real-time as well as multiple cluster environments. In addition, we make use of JPEG compression and RAM disk method for better performance. Our scheme first converts input images from 4 channel, 16 cameras to binary image. And then we generate 3D stereo images after applying edge detection algorithm such as Sobel algorithm and Prewiit algorithm used to get disparities from images of 16 multiple cameras. With respect of performance results, the proposed scheme takes about 0.05 sec. to transfer image from client to server as well as 0.84 to generate 3D stereo images after composing 2D images from 16 multiple cameras. We finally confirm that our scheme is efficient to generate 3D stereo images in multiple view and multiple clusters environments with real-time.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.109-114
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• 2011

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.

• Journal of the Korean Vacuum Society
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• v.7 no.4
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• pp.368-373
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• 1998

As device dimensions approach submicrometer size in ULSI, the demand for interlayer dielectric materials with very low dielectric constant is increased to solve problems of RC delay caused by increase in parasitic resistance and capacitance in multilevel interconnectins. Fluorinated amorphous carbon in one of the promising materials in ULSI for the interlayer dielectric films with low dielectric constant. However, poor thermal stability and adhesion with Si substrates have inhibited its use. Recently, amorphous hydrogenated carbon (a-C:H) film as a buffer layer between the Si substrate and a-C:F has been introduced because it improves the adhesion with Si substrate. In this study, therfore, a-C:F/a-C:H films were deposited on p-type Si(100) by ECRCVD from $C_2F_6, CH_4$and $H_2$gas source and investigated the effect of forward power and composition on the thickness, chemical bonding state, dielectric constant, surface morphology and roughness of a-C:F films as an interlayer dielectric for ULSI. SEM, FT-IR, XPS, C-V meter and AFM were used for determination of each properties. The dielectric constant in the a-C:F/a-C:H films were found to decrease with increasing fluorine content. However, the dielectric constant increased after furnace annealing in $N_2$atomosphere at $400^{\circ}C$ for 1hour due to decreasing of flurorine content. However, the dielectric constant increased after furnace annealing in $N_2$atmosphere at $400^{\circ}C$ for 1hour due to decreasing of fluorine concentration.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.2
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• pp.299-306
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• 2016

In this paper, a method of shape prediction of an endoscope handling robot that can imitate a surgeon's behavior using a sensor network is suggested. Unit sensors, which are composed of a 3-axis magnetometer and 3-axis accelerometer pair comprise the network through CAN bus communication. Each unit of the sensor is used to detect the angle of the points in the longitudinal direction of the robot, which is made from a flexible tube. The signals received from the sensor network were filtered using a low pass Butterworth filter. Here, a Butterworth filter was designed for noise removal. Finally, the Euler angles were extracted from the signals, in which the noise was filtered by the low path Butterworth filter. Using this Euler angle, the position of each sensor on the sensor network is estimated. The robot body was assumed to consist of links and joints. The position of each sensor can be assumed to be attached to the center of each link. The position of each link was determined using the Euler angle and kinematics equation. The interpolation was carried out between the positions of the sensors to be able to connect each point smoothly and obtain the final posture of the endoscope in operation. The experimental results showed that the shape of the colonoscope can be visualized using the Euler angles evaluated from the sensor network suggested and the shape of serial link estimated from the kinematics chain model.