• Proceedings of the Korea Information Processing Society Conference
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• 2011.04a
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• pp.194-196
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• 2011

일반적으로 센서 네트워크에서는 라우팅 트리를 구축한 후에 시간 동기화 작업을 따로 진행하였다. 그 때문에 패킷교환의 횟수가 늘어나고 전력의 소모를 유발한다. 본 논문에서는 라우팅 트리 구축과정에서 교환하는 정방향과 역방향의 패킷에 LTS(Lightweight Time Synchronization) 알고리즘 연산에 필요한 시간정보를 추가하여 플러딩 라우팅 트리 구축 알고리즘과 시간 동기화 과정을 결합한 알고리즘을 제안한다. 또한 일정한 라운드 시간을 사용하여 클럭 휨으로 인한 시간 오류를 보정하였다. 제안하는 알고리즘이 TPSN(Timing-sync Protocol for Sensor Networks) 방식보다 적은 에너지를 사용하고 센서 노드들 간의 시간을 더욱 정교하게 동기화한다는 것을 NS2 시뮬레이터를 통해서 증명하였다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.3
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• pp.896-905
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• 2010

The sensor networks can be used attractively for various application areas. Time synchronization is important for any Ubiquitous Sensor Networks (USN) systems. USN makes extensive use of synchronized time in many contexts for data fusion. However existing time synchronization protocols are available only for homogeneous sensor nodes of USN. It needs to be extended or redesigned in order to apply to the USN with heterogeneous sensor nodes. Because heterogeneous sensor nodes have different clock sources with the SinkNode of USN, it is impossible to be synchronized global time. In addition, energy efficiency is one of the most significant factors to influence the design of sensor networks, as sensor nodes are limited in power, computational capacity, and memory. In this paper, we propose specific time synchronization based on master-slave topology for the global time synchronization of USN with heterogeneous sensor nodes. The time synchronization master nodes are always able to be synchronized with the SinkNode. Then time synchronization master nodes enable time synchronization slave nodes to be synchronized sleep periods. The proposed master-slave time synchronization for heterogeneous sensor nodes of USN is also helpful for power saving by maintaining maximum sleep time.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1277-1281
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• 2005

FPGA has been widely used in communication system. In this paper, we made 10 layers PCB on protection of signal noise and data lose with FPGA. We analyzed about change of the data transmission speed and length according to input frequency. The length of transmission line from FPGA's output-pin to output-port on PCB board is 13cm and extended lengths for test are 30cm, 60cm and 10cm. We knew that data can be stably transmitted to 100Mbps at transmission line length of 30cm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.7C
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• pp.608-615
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• 2007

Generally time of arrival (TOA) information via two way communications can be derived by accurate round trip time (RTT) between two devices. However, response time demanded in RTT measurement is long, a serious TOA error is caused by each different clock drift between two devices. In order to solve this problem, we propose the TOA and time difference of arrival (TDOA) estimation scheme with mitigating clock drift effect. To verify the performance of proposed method, we compared the proposed scheme with one way based TDOA acquisition method introduced by IEEE 802.15.4a Task Group and then we could conclude that the proposed method has better performance over other methods.

• The KIPS Transactions:PartC
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• v.19C no.3
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• pp.209-214
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• 2012

Time synchronization is important role in a network, especially in Wireless Sensor Network (WSN) which is required for time-critical applications such as surveillance, tracking, data fusion and scheduling. Time synchronization in WSN should meet the other different requirements than the one in other networks because WSN has critical resource constraints, especially power consumption. This paper presents a new time synchronization scheme for WSN, which is energy efficient by reducing communication overhead. Simulation test shows this new scheme has better energy efficiency and performance of accuracy than existing schemes proposed previously.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.423-429
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• 2007

The clock recovery module of gap filler for satellite DMB is proposed. Proposed module sustains the output frequency of 10 MHz whether the received signal from the satellite is unstable or cut off within 0.5 sec. The advantages of this module is without frequency tuning at regular interval and low material cost. This module is fabricated by using CPLD as clock recovery IC and new type of loop filter for satisfying the fast lock time and long hold over time simultaneously. The measured performance of the fabricated module has a holdover time of 11 sec at frequency stability less than 0.01 ppm, and phase noise of -113 dBc/Hz at 100 Hz offset.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.90-96
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• 2014

This paper presents a practical linearization technique for a wide-band bang-bang digital phase locked-loop(BBDPLL) by selecting optimal loop gains. In this paper, limitation of the theoretical design method for BBDPLL is explained, and introduced how to implement practical BBDPLLs with CMOS process. In the proposed BBDPLL, the limited cycle noise is removed by reducing the proportional gain while increasing the integer array and dither gain. Comparing to the conventional BBDPLL, the proposed one shows a small area, low power, linear characteristic. Moreover, the proposed design technique can control a loop bandwidth of the BBDPLL. Performance of the proposed BBDPLL is verified using CppSim simulator.

• The KIPS Transactions:PartC
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• v.18C no.2
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• pp.119-126
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• 2011

In wireless sensor networks Time synchronization used to be performed after routing tree is constructed. It results in increasing the number of packets and energy consumption. In this paper, we propose a time synchronization algorithm combined with flooding routing tree construction algorithm, which applies LTS (Lightweight Time Synchronization) information packed into the forwarding and backward routing packets. Furthermore, the proposed algorithm compensates the time error due to clock drift using the round time with fixed period. We prove that the proposed algorithm could synchronize the time of among sensor nodes more accurately compared to TSRA (Time Synchronization Routing Algorithm) using NS2 simulation tool.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.3
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• pp.53-64
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• 1997

When we apply a synchronous stream cipher to the T1 carrier system, it can occur long consecutive 0's(or 1's) sequences in the received data. In this case, it is difficult to recover receiver clock and violates a communication protocol. This paper proposes block detection and serial detection method which suppress 0's sequences of more than k( $\geq$ 2) of the stream ciphertext in the T1 carrier system. These ZS methods keep security level and solve problems of stream synchronization.