• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.4
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• pp.53-58
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• 2008

This paper designs sigma-delta D/A Converter with a high resolution and low power consumption. It reorganizes the input data along LJ, RJ, I2S mode and bit mode to the output data of A/D converter. The D/A converter decodes the original analog signal through HBF, Hold and 5th CIFB(Cascaded Integrators with distributed Feedback as well as distributed input coupling) sigma-delta modulation blocks. It uses repeatedly the addition operation in instead of the multiply operation for the chip area and the performance. Also, the half band filters of similar architecture composed the one block and it used the sample-hold block instead of the sinc filter. We supposed simple D/A Converter decreased in area. The filters of the block analyzed using the matlab tool. The top block designed using the top-down method by verilog language. The designed block is fabricated using Samsung 0.35um CMOS standard cell library. The chip area is 1500*1500um.

• The Journal of the Convergence on Culture Technology
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• v.6 no.3
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• pp.427-430
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• 2020

The multi-channel analog signal to digital signal conversion is increasing in the field of IoT and medical measurement equipments. It has chip area and power consumption constraints to use a few single or 2_channel ADC for multi_channel application. This paper described to design and implement a proposed comb filter for multi-channel, 24bit ADC. The function of proposed comb filter is verified by matlab simulation and the FPGA test board. It was fabricated using SK Hynix 0.35㎛ CMOS standard process. The performance and chip size is compared with the existing design method that uses integrator/differentiator and FIR construction. The proposed comb filter is expected to use the IoT product and medical measurement equipments that require multi-channel, low power consumption and small hardware size.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.6-14
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• 2011

This paper presents the design of the battery sensor IC for instrumentation of current, voltage using delta-sigma ADC. The proposed circuit consists of programmable gain instrumentation amplifier (PGIA) and second-order discrete-time delta-sigma modulator with 1-bit quantization were fabricated by a 0.25 ${\mu}m$ CMOS technology. Design circuit show that the modulator achieves 82 dB signal-to-noise ratio (SNR) over a 2 kHz signal bandwidth with an oversampling ratio (OSR) of 256 and differential nonlinearity (DNL) of ${\pm}$ 0.3 LSB, integral nonlinearity (INL) of ${\pm}$ 0.5 LSB. Power consumption is 4.5 mW.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.2
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• pp.151-155
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• 2016

In this paper, we present the LED dimming control system by using ADPCM (Adaptive Differential Pulse Code Modulation). This ADPCM apparatus accurately controls the LED current with high resolution reducing the RFI (radio frequency interference) due to the spreading out of the harmonics of current of pulses. Additionally, this makes it easier to increase the accuracy of control operation. This study introduces to make a digitally controlled circuit for controlling LED with high-energy efficient by adopting pulse current to LED. The LED current drive system we designed are two systems, the digitally-controlled unit and analog switching mode power supply unit, can be developed separately. The simulation shows the sigma delta modulation of digital to analog converter's output when the input level is 0.7. From this simulation, the output is approached to accurately 0.15% to target value with 510 pulses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.64-72
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• 2010

This paper presents a wide range VCO with fine coarse tuning step using a sigma-delta modulation technique for UWB frequency synthesizer. The proposed coarse tuning scheme provides the low effective frequency resolution without any degradation of phase noise performance. With three steps coarse tuning, the VCO has wide tuning range and fine tuning step simultaneously. The frequency synthesizer with VCO was implemented with 0.13 ${\mu}m$ CMOS technology. The tuning range of the VCO is 5.8 GHz~6.8 GHz with the effective frequency resolution of 3.9 kHz. It achieves the measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range 16.8 % with 5.9 mW power. The figure-of-merit with the tuning range is -181.5 dBc/Hz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.28-36
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• 2008

This paper discusses theimplementation of the low-voltage, low-power, third-order, 1-bit switched capacitor delta-sigma modulator of the implantable cardiac pacemaker. The distributed, feed-forward structure and bulk-driven OTA were used in order to achieve an efficient operation under a supply voltage of 1V or lower. The designed modulator has a dynamic range of 49dB at 0.9V supply voltage and consumes 816nW of power. Such a significant reduction in power consumption allows diverse applications, not only in pacemakers, but also in implantable biomedical devices that operate with limited battery power. The core chip size of the modulator is $1000{\mu}m*500{\mu}m$ manufactured, with the $0.18{\mu}m$ CMOS standard process.

• Journal of IKEEE
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• v.21 no.4
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• pp.331-337
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• 2017

In this paper, we present the design of a 20MHz bandwidth 3rd-order continuous-time low-pass sigma-delta modulator with low-noise and low-power consumption. The bandwidth of the system is sufficient to accommodate LTE and other wireless network standards. The 3rd-order low-pass filter with feed-forward architecture achieves the low-power consumption as well as the low complexity. The system uses 3bit flash quantizer to provide fast data conversion. The current-steering DAC achieves low-power and improved sensitivity without additional circuitries. Cross-coupled transistors are adopted to reduce the current glitches. The proposed system achieves a peak SNDR of 65.9dB with 20MHz bandwidth and power consumption of 32.65mW. The in-band IM3 is simulated to be 69dBc with 600mVp-p two tone input tones. The circuit is designed in a 0.18-um CMOS technology and is driven by 500MHz sampling rate signal.

• Journal of IKEEE
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• v.26 no.2
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• pp.299-305
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• 2022

Analog-digital converter (ADC) should be one of the most important blocks that convert various physical signals to digital ones for signal processing in the digital signal domain. As most operations of the analog circuit for sensor signal processing have been replaced by digital circuits, high-resolution performance is required for ADC. In addition, low-power must be the critical issue in order to extend the battery time of mobile system. The existing integrating sigma-delta ADCs has a characteristic of high resolution, but due to its low supply voltage condition and advanced technology, circuit error and corresponding resolution degradation of ADC result from the finite gain of the operational amplifier in the integrator. Buffer compensation technique can be applied to minimize gain errors, but there is a disadvantage of additional power dissipation due to the added buffer. In this paper, incremental signal-delta ADC is proposed with buffer switching scheme to minimize current and igh-pass bias circuit to improve the settling time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1619-1626
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• 2021

Unlike traditional delta-sigma analog-to-digital converters, incremental analog-to-digital converters enable 1:1 mapping of input and output through a reset operation, which can be used very easily for multiplexing. Incremental analog-to-digital converters also allow for simpler digital filter designs compared to traditional delta-sigma converters. Therefore, starting with analysis in the time domain of the delayed integrator and non-delayed integrator, which are the basic blocks of analog-to-digital converter design, the design equations of a second-order input feed-forward, extended counting, 2+1 MASH (Multi-stAge-noise-SHaping), 2+2 MASH incremental analog-to-digital converter are derived in this paper. This allows not only prediction of the performance of the incremental analog-to-digital converter before design, but also the design of a digital filter suitable for each analog-to-digital converter. In addition, extended counting and MASH design techniques were proposed to improve the accuracy of analog-to-digital converters.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.5
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• pp.335-342
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• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.