• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.637-637
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• 1997

In this paper, format conversion filters are proposed, which have advantages in hardware implementation compared to the ones proposed in MPEG-4 Video Verification Model. since each coefficients of the proposed filters is constrained to have less than two non-zero digits in minimal signed digit representation, multiplication of input and the coefficient can be implemented by a single adder. As a result, the proposed filters have advantages in hardware complexity and speed, compared to the filters which are usually implemented by integer multiplier or carry save adders. Six kinds of filters are proposed in MPEG-4 Video Verification Model for size conversion of 2:1, 4:1, 5:3 and 5:6. We design 5 filters for the same purpose and compare the performance. The remaining one is very simple to implement. For comparing the filtering performance, we first compare the results of sine wave frequency conversion as an indirect but meaningful comparison. Second. We compute the PSNR of the images obtained from the proposed filters and the ones proposed by MPEG, with reference to the images obtained by using double precision arithmetic and high order filter. The results show that the performance of the proposed filters is almost the same as that of the filters proposed by MPEG. In conclusion, the peroformance of the proposed filters is comparable to that of the ones in MPEG-4, while requiring lower hardware complexity and providing high operating speed.

• Journal of Elementary Mathematics Education in Korea
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• v.7 no.1
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• pp.45-64
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• 2003

This study analyzes divisor and multiple in elementary school mathematics textbooks published according to the first to the 7th curriculum, in a view point of the didactic transposition theory. In the first and second textbooks, the divisor and the multiple are taught in the chapter whose subject is on the calculations of the fractions. In the third and fourth textbooks, divisor and multiple became an independent chapter but instructed with the concept of set theory. In the fifth, the sixth, and the seventh textbooks, not only divisor multiple was educated as an independent chapter but also began to be instructed without any conjunction with set theory or a fractions. Especially, in the seventh textbook, the understanding through activities of students itself are strongly emphasized. The analysis on the each curriculum periods shows that the divisor and the multiple and the reduction of a fractions to the lowest terms and to a common denominator are treated at the same period. Learning activity elements are increase steadily as the textbooks and the mathematical systems are revised. The following conclusion can be deduced based on the textbook analysis and discussion for each curriculum periods. First, loaming instruction method also developed systematically with time. Second, teaching method of the divisor and multiple has been sophisticated during the 1st to 7th curriculum textbooks. And the variation of the teaching sequences of the divisor and multiple is identified. Third, we must present concrete models in real life and construct textbooks for students to abstract the concepts by themselves. Fourth, it is necessary to develop some didactics for students' contextualization and personalization of the greatest common divisor and least common multiple. Fifth, the 7th curriculum textbooks emphasize inquiries in real life which teaming activities by the student himself or herself.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.11-20
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• 2007

A fast Montgomery multiplication occupies important to the design of RSA cryptosystem. Montgomery multiplication consists of two addition, which calculates using CSA or RBA. In terms of CSA, the multiplier is implemented using 4-2 CSA o. 5-2 CSA. In terms of RBA, the multiplier is designed based on redundant binary system. In [1], A new redundant binary adder that performs the addition between two binary signed-digit numbers and apply to Montgomery multiplier was proposed. In this paper, we reconstruct the logic structure of the RBA in [1] for reducing time and space complexity. Especially, the proposed RB multiplier has no coupler like the RBA in [1]. And the proposed RB multiplier is suited to binary exponentiation as modified input and output forms. We simulate to the proposed NRBA using gates provided from SAMSUNG STD130 $0.18{\mu}m$ 1.8V CMOS Standard Cell Library. The result is smaller by 18.5%, 6.3% and faster by 25.24%, 14% than 4-2 CSA, existing RBA, respectively. And Especially, the result is smaller by 44.3% and faster by 2.8% than the RBA in [1].