• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.724-727
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.1976-1979
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• 2008

Studies on binary adder have been variously developed. According to those studies of critical worst delay and mean delay time of asynchronous binary adders, carry select adders (CSA) based on hybrid structure showed 17% better performance than ripple carry adders (RCA) in 32 bit asynchronous processors, and 23% better than in 64 bit microprocessor implemented. In the complicated signal processing systems such as RSA, it is essential to optimize the performance of binary adders which play fundamental roles. The researches which have been studied so far were subject mostly to addition algorithms or adder structures. In this study, we analyzed and designed adders in an asp;ect of synthesis method. We divided the ways of implementing adders into groups, each of which was synthesized with different synthesis options. Also, we analyzed the variously implemented adders to evaluate the performance and area so that we can propose a different approach of designing optimal binary adders.

• Communications of Mathematical Education
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• v.23 no.3
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• pp.707-734
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• 2009

The purpose of the study was to investigate how children understand addition and subtraction of fractions and how their understanding influences the solutions of fractional word problems. Twenty students from 4th to 6th grades were involved in the study. Children's understanding of operations with fractions was categorized into "joining", "combine" and "computational procedures (of fraction addition)" for additions, "taking away", "comparison" and "computational procedures (of fraction subtraction)" for subtractions. Most children understood additions as combining two distinct sets and subtractions as removing a subset from a given set. In addition, whether fractions had common denominators or not did not affect how they interpret operations with fractions. Some children understood the meanings for addition and subtraction of fractions as computational procedures of each operation without associating these operations with the particular situations (e.g. joining, taking away). More children understood addition and subtraction of fractions as a computational procedure when two fractions had different denominators. In case of addition, children's semantic structure of fractional addition did not influence how they solve the word problems. Furthermore, we could not find any common features among children with the same understanding of fractional addition while solving the fractional word problems. In case of subtraction, on the other hand, most children revealed a tendency to solve the word problems based on their semantic structure of the fractional subtraction. Children with the same understanding of fractional subtraction showed some commonalities while solving word problems in comparison to solving word problems involving addition of fractions. Particularly, some children who understood the meaning for addition and subtraction of fractions as computational procedures of each operation could not successfully solve the word problems with fractions compared to other children.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 1995.11a
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• pp.151-162
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• 1995

보다 짧은 길이의 덧셈/뺄셈 사슬($addition_{traction-chain}$)을 찾는 문제는 정수론을 기반으로 하는 많은 암호시스템들에 있어서 중요한 문제이다. 특히, RSA에서의 모듈라멱승(modular exponentiation)이나 타원 곡선(elliptic curve)에서의 곱셈 연산시간은 덧셈사슬(addition-chain) 또는 덧셈/뺄셈 사슬의 길이와 정비례한다 본 논문에서는 덧셈/뻘셈 사슬을 구하는 새로운 알고리즘을 제안하고, 그 성능을 분석하여 기존의 방법들과 비교한다. 본 논문에서 제안하는 알고리즘은 작은윈도우(small-window) 기법을 기반으로 하고, 뺄셈을사용해서 윈도우의 개수를 최적화함으로써 덧셈/뺄셈 사슬의 길이를 짧게 한다. 본 논문에서 제안하는 알고리즘은 512비트의 정수에 대해 평균길이 595.6의 덧셈/뺄셈 사슬을 찾는다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.691-693
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• 2004

0.18$\mu\textrm{m}$ 표준 셀 라이브러리로 구현할 때 2.69㎱의 임계 경로 지연을 가지는 SIMD구조의 포화 덧셈기를 설계하였다. 기존의 설계에서 임계 경로를 구성하는 CLA를, 8비트까지만 자리올림(Carry)이 전파될 때 정확한 계산을 보장하는 근사 덧셈기의 형태로 설계한 결과, 임계 경로 시간 지연을 약 22% 감소시킬 수 있었다. 파이프라인 구조 프로세서에서 사용될 포화 덧셈기의 근사계산이 실패하는 경우에는, 추가적인 2개의 클록주기 동안 재 계산을 수행하게 된다.

• School Mathematics
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• v.18 no.1
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• pp.175-191
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• 2016

In the elementary school mathematics textbook that has been revised in 2013, the instructional sequence for teaching addition and subtraction, which had remained unchanged for three decades since 1982, was finally changed in 2013. Particularly, the addition and subtraction of two-digit numbers without regrouping, such as 72+25=97 or 85-24=61, are taught earlier than the composing and decomposing of the number 10 using other numbers. This study examines the appropriacy and validity of these changes. However, the reason for these changes in the national curriculum or teacher's guide could not be determined. Further, several references emphasize the addition of two single-digit numbers, such as 7+8=15, and the subtraction of a single-digit number from a number between 11 and 19, such as 16-9=7, as basic facts. In other countries' textbooks, the teaching of addition and subtraction up to the number 20 is prioritized before teaching the addition and subtraction of two-digit numbers without regrouping. The results of this study indicate that these changes in the instructional sequence in the textbook that was revised in 2013 need to be reconsidered.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.32-36
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• 2008

Multiplierless FIR filters can be designed by only adders using Common Subexpression algorithm. It has small area compared with filter which using multipliers. But it has long operation time because of carry ripple from the adder. In this paper, when the subexpressions are added in multiplier less filters, the number of subexpressions maintains 2 until final addition to avoid carry ripple of the addition, so the subexpression addition time of the filter can be reduced. To verify proposed method, subexpression adder circuit of the FIR filter is designed using given example of paper. The designed filter was synthesized using Hynix 0.18um process. By Synopsys simulation results, it is shown that by the proposed method, area, propagation delay time can be reduced up to 53.2%, 57.9% compared with conventional design method which using pipeline.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.5
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• pp.55-65
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• 2000

In this paper a new architecture of 24-bit two's complement adder is designed by using RB(Redundant Binary) arithmetic which has the advantage of CPF(Carry-Propagation-Free). A MPPL(Modified PPL) XOR/XNOR gate is applied to improve a TC2RB(Two's Complement to RB SUM converter) speed and to reduce the number of transistors, and we proposed two types adder which used a fast RB2TC(RB SUM to Two's Complement converter). The property of two types adder is followings. The improvement of TYPE 1 adder speed is archived through the use of VGS(Variable Group Select) method and TYPE 2 adder is through the use of a 64-bit GCG(Group Change bit Generator) circuit and a 8-bit TYPE 1 adder. For 64-bit, TYPE 1 adder can be expected speed improvement of 23.5%, 25.7% comparing with the CLA and CSA, and TYPE 2 adder can be expected 41.2%, 45.9% respectively. The propagation delay of designed 24-bit TYPE 1 adder is 1.4ns and TYPE 2 adder is 1.2ns. The implementation is highly regular with repeated modules and is very well suited for microprocessor systems and fast DSP units.

• School Mathematics
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• v.18 no.4
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• pp.793-818
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• 2016

The purpose of this study is to explore in detail $5^{th}$ grade students' understanding on the big ideas related to addition of fraction with different denominators: fixed whole unit, necessity of common measure, and recursive partitioning connected to algorithms. We conducted teaching experiments on 15 fifth grade students who had learned about addition of fractions with different denominators using the current textbook. Most students approached to the big ideas related to addition of fractions in a procedural way. However, some students were able to conceptually understand the interpretations and algorithms of fraction addition by quantitatively thinking about the context and focusing on the structures of units. Building on these results, this study is expected to suggest specific implications on instruction methods for addition of fractions with different denominators.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.12B
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• pp.2052-2059
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• 2000

Digital IF(Intermediate Frequency) 처리단과 같은 고속과 저전력을 요구하는 필터에서 덧셈기만을 사용하여 CSD(Canonical Signed Digit)형의 필터계수들을 구현하는 구조가 널리 연구되고 있다. 본 논문에서는 선형위상 FIR(Finite Impulse Response) 필터의 CSD형 필터계수들을 최소의 덧셈으로 구현할 수 있는 아키텍처를 제안한다. 1과 -1로 이루어진 필터계수 표에서 공통패턴을 공유함으로서 덧셈의 수를 줄이는 방법이 이미 연구되었다. 본 논문은 비트 shift, 비트 add, 비트 반전을 통하여 인공의 공통패턴을 만들어서 이미 존재하는 공통패턴에 합류시킴으로서 덧셈의 수를 더욱 줄일 수 있는 방법을 제안한다. CDMA 이동통신 단말기의 IF단에 사용되는 사양의 디지털 필터를 73탭의 CSD형 계수로 구현하여 9.2%의 덧셈 감소의 효과가 있음을 보였다.