• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.2
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• pp.251-258
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• 2023

In this paper, we propose DLP(Dual Linear Polarization) stack antenna for private network. The proposed antenna has general stack structure and design airgap between two substrate to obtain the maximum gain. Also, to improve cross polarization isolation, two feeding port is designed to separate for each substrate. The size of each patch antenna is 17.80 mm(W1)×16.70 mm(L1) for lower patch and 18.56 mm(W2)×18.73 mm(L2) for upper patch, which is designed on the FR-4 substrate which thickness (h) is 1.6 mm, and the dielectric constant is 4.3, and which is 40.0 mm(W)×40.0 mm(L) for total size of substrate. From the fabrication and measurement results, bandwidths of 100 MHz (4.74 to 4.84 GHz) for feeding port 1, and 150 MHz (4.67 to 4.82 GHz) for feeding port 2 are obtained on the basis of -10 dB return loss and transmission coefficient S21 is got under the -20 dB. Also, cross polarization isolation between each feeding port obtained

• Journal of Advanced Navigation Technology
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• v.25 no.6
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• pp.536-542
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• 2021

In this paper, we proposed a triple band printed monopole antenna with a bent branch strips for WiFi / 5G. An antenna structure in which bent strips for generating multiple resonance are attached in the form of branches was newly proposed based on a typical monopole strip vertically erected as a triple band antenna structure. The proposed antenna is designed on a FR-4 substrate with dielectric constant 4.3, thickness of 1.6 mm, and size of 28×40 mm². The measured impedance bandwidth is 430 MHz (2.22~2.65 GHz) in the 2.4 GHz WLAN, 450 MHz (3.38~3.83 GHz) in the 3.5 GHz and 2390 MHz (4.95~7.34 GHz), In particular, it has been observed that antenna has a stable omnidirectional radiation patterns as well as gain of 1.537 dBi, 1.878 dBi and 2.337 dBi in the entire frequency band of interest.

• Journal of Advanced Navigation Technology
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• v.27 no.4
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• pp.447-452
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• 2023

In this paper, gain enhancement of a double dipole quasi-Yagi antenna using a meanderline array structure was studied. A 4×1 meanderline array structure consisting of a meanderline conductor- shaped unit cell is located above the second dipole of the double dipole quasi-Yagi antenna. It was designed to have gain over 7 dBi in the frequency range between 1.70 and 2.70 GHz in order to compare the performance with the case using a conventional strip director. As a result of comparison, the average gain of the double dipole quasi-yagi antenna with the proposed meander line array structure was larger compared to the case with the conventional strip director. A double dipole quasi-Yagi antenna using the proposed meanderline array structure was fabricated on an FR4 substrate and its characteristics were compared with the simulation results. Experiment results show that the frequency band for a VSWR less than 2 was 1.55-2.82 GHz, and the frequency band for gain over 7 dBi was measured to be 1.54-2.83 GHz. The frequency bandwidth with gain over 7 dBi increased, and average gain also slightly increased, compared to the conventional case using a strip director.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.6
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• pp.1015-1022
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• 2023

In this paper, we propose DLP(Dual Linear Polarization) antenna with aperture coupled feeding structure for private network. The proposed antenna has general aperture coupled structure and design two port between top and bottom layer to obtain the enhanced isolation. Also, The size of each substrate(top and bottom layer) is 34.0 mm(W)×34.0 mm(L), which is designed on the FR-4 substrate which thickness (h) is 1.0 mm, and the dielectric constant is 4.4. Also, the size of patch antenna is 12.70 mm(W2)×14.60 mm(L3), and it is located on the top layer. The size of feeding line is 24.0 mm(W2)×1.6 mm(L3), and is located at the bottom layer Also, rectangular slot is located on the ground plane between top layer and bottom layer. From the fabrication and measurement results, bandwidths of 300 MHz (4.52 to 4.82 GHz) for feeding port 1, and 170 MHz (4.65 to 4.82 GHz) for feeding port 2 are obtained on the basis of -10 dB return loss and transmission coefficient S21 is got under the -30 dB. Also, cross polarization isolation between each feeding port obtained

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.122-130
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• 2013

This work proposes a 12b 100MS/s 45nm CMOS four-step pipeline ADC for high-speed digital communication systems requiring high resolution, low power, and small size. The input SHA employs a gate-bootstrapping circuit to sample wide-band input signals with an accuracy of 12 bits or more. The input SHA and MDACs adopt two-stage op-amps with a gain-boosting technique to achieve the required DC gain and high signal swing range. In addition, cascode and Miller frequency-compensation techniques are selectively used for wide bandwidth and stable signal settling. The cascode current mirror minimizes current mismatch by channel length modulation and supply variation. The finger width of current mirrors and amplifiers is laid out in the same size to reduce device mismatch. The proposed supply- and temperature-insensitive current and voltage references are implemented on chip with optional off-chip reference voltages for various system applications. The prototype ADC in a 45nm CMOS demonstrates the measured DNL and INL within 0.88LSB and 1.46LSB, respectively. The ADC shows a maximum SNDR of 61.0dB and a maximum SFDR of 74.9dB at 100MS/s, respectively. The ADC with an active die area of $0.43mm^2$ consumes 29.8mW at 100MS/s and a 1.1V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.58-68
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• 2006

This work proposes a 10b 250MS/s $1.8mm^2$ 85mW 0.13um CMOS A/D Converter (ADC) for high-performance integrated systems such as next-generation DTV and WLAN simultaneously requiring low voltage, low power, and small area at high speed. The proposed 3-stage pipeline ADC minimizes chip area and power dissipation at the target resolution and sampling rate. The input SHA maintains 10b resolution with either gate-bootstrapped sampling switches or nominal CMOS sampling switches. The SHA and two MDACs based on a conventional 2-stage amplifier employ optimized trans-conductance ratios of two amplifier stages to achieve the required DC gain, bandwidth, and phase margin. The proposed signal insensitive 3-D fully symmetric capacitor layout reduces the device mismatch of two MDACs. The low-noise on-chip current and voltage references can choose optional off-chip voltage references. The prototype ADC is implemented in a 0.13um 1P8M CMOS process. The measured DNL and INL are within 0.24LSB and 0.35LSB while the ADC shows a maximum SNDR of 54dB and 48dB and a maximum SFDR of 67dB and 61dB at 200MS/s and 250MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 85mW at 250MS/s at a 1.2V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.31-38
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• 2008

Ad-Hoc network is a network architecture which has no backbone network and is deployed temporarily and rapidly in emergency or war without fixed mobile infrastructures. All communications between network entities are carried in ad-hoc networks over the wireless medium. Due to the radio communications being extremely vulnerable to propagation impairments, connectivity between network nodes is not guaranteed. Therefore, many new algorithms have been studied recently. This study proposes the secondary header approach to the cluster based routing protocol (CBRP). The primary header becomes abnormal status so that the primary header can not participate in the communications between network entities, the secondary header immediately replaces the primary header without selecting process of the new primary header. This improves the routing interruption problem that occurs when a header is moving out from a cluster or in the abnormal status. The performances of proposed algorithm ACBRP(Advanced Cluster Based Routing Protocol) are compared with CBRP. The cost of the primary header reelection of ACBRP is simulated. And results are presented in order to show the effectiveness of the algorithm.