• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.377-378
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• 2007

본 논문에서는 저전력 임베디드 시스템을 위한 효율적인 다중 NAND 플래쉬 파일 시스템을 제안한다. 기존에 제안되었던 하드디스크를 비롯한 저장 장치들과는 달리 NAND 플래쉬 메모리는 특정 블록에 쓰기 연산을 하기 전에 해당 블록은 이미 소거된 상태이어야 한다. 또한 이러한 소거의 횟수는 각 블록마다 제한적이다. 이러한 문제를 해결하기 위해서 소거 횟수 평준화 기법이 많이 사용되고 있고 관련하여 많은 연구가 진행되고 있다. 본 논문에서는 소거 횟수에 임계치를 설정하여 연산하는 방법을 제안한다. 또한 기존에는 단일 플래쉬 메모리만을 고려하고 있으나 본 논문에서는 다중 플래쉬 메모리 구조를 고려한다.

• Journal of the Korean Solar Energy Society
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• v.28 no.5
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• pp.1-7
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• 2008

Flashed steam system is one of the important geothermal power production methods. In this paper, optimum operations and performances of single and double flash systems are presented. It is shown that double flash system can produce about 26.5% more power than single flash system. Temperature of geothermal water($T_R$) is the most important parameter in the geothermal system. Optimum single and double flash temperatures and net power produced with these optimum conditions are expressed as a function of $T_R$ in this study. Thus net power output from geothermal resources can be estimated with the results of this work. Condenser Temperature($T_{con}$) is also important and the net power production can be shown as a function of ($T_R-T_{con}$. Volume flow rate per unit power is also to be considered as the condenser temperature decreases.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.1
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• pp.17-24
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• 2012

There has been little study on the performance characteristics of the effective heat pump systems in the cooling mode using the two-stage compression cycles have hardly performed. In this study, the performance of the two-stage compression $CO_2$ cycle with an FI (flash intercooler) and the FGB (flash gas bypass) was investigated by using a theoretical method. The performance analysis was carried out with aby varyingiation (the indoor temperature, outdoor temperature, and 1st- and 2nd-stage EEV openings. As of a result, the coefficients of performance (COPs) of the Bbasic, FI, and FGB cycles were decreased by 28.5%, 22.1%, and 24.5%, respectively, for various outdoor temperature conditions. In addition to, the performance variation of the two-stage compression cycle was smaller than that of the single-stage compression cycle. The performance of the FI and FGB cycles was improved by 13.5%, and 6.9%, respectively, when the 1st-stage EEV opening was increased from 32% to 48%, and by 0.9%, and 2.6%, respectively, when the 1st- andthe 2nd-stage EEV opening was increased from 32% to 48%, andwas increased from 42% to 58%, respectively. The FI cycle showed anthe most improved performance for any given operating conditions.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.5A
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• pp.504-512
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• 2010

The paper proposes the 6bit 800MS/s flash A/D converter that can be applied to wireless USB chip-set. The paper simplified the error correction circuit and synchronization block as one circuit which are used respectively, and furthermore reduced the burden on the hardware. Comparing to the conventional error correction circuit, the proposed error correction circuit in this paper reduced 5 MOS transistors, the area of each error correction circuit is reduced by 9%. The A/D converter is fabricated with 0.18um CMOS 1-poly 6-metal process, and power dissipation is 182mW at 0.8Vpp input range and 1.8V supply voltage. The measured result shows 4.0bit of ENOB at 800MS/s conversion rate and 128.1MHz input frequency.

• Journal of the Korea Computer Industry Society
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• v.2 no.3
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• pp.369-376
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• 2001

The optimization of resonator and laser power supply has been considered to be significant for improving the efficiency of a pulsed Nd:YAG laser system. We have proposed a new method of 3-mesh parallel sequential charge and discharge circuit as a laser power supply; more compact than conventional power supply, competitive in price, easy to control the laser power density according to various material processing, and equipped with the optimum reflectivity of output coupler. In this study, we could find that the maximum laser output was obtained by using 85% of reflectivity in the case of 50[W]-class. In addition using the power supply of new method, it's possible to charge each capacitor bank with a higher energy within the given charging time adopted a new method mentioned above; namely, we can allow each capacitor to have much more charging time and storage energy. So, higher laser output was obtained than conventional power supply.