• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.111-119
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• 1997

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently used in constructing the digital logic systems based on the graph theory. And we discussed the function minimization method of the n-variables multiple-valued functions. The proposed method has the visible, schematical and regular properties.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.22-32
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• 2004

In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1851-1864
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• 1997

This paper presents an algorithm simplifying the ESOP function by several rules. The algorithm is repeatedly performing operations based on the state of each terms by the product transformation operation of two functions and thus it is simplifying the ESOP function through the reduction of the product terms. Through the minimization of the product terms of the multi-valued input binary multi-output function, an optimization of the input has been done using EXOR PLA with input decoder. The algorithm when applied to four valued arithmetic circuit has been used for a EXOR logic circuit design and the two bits input decoder has been used for a EXOR-PLA design. It has been found from a computer simulation(IBM PC486) that the suggested algorithm can reduce the product terms of the output function remarkably regardless of the number of input variables when the variable AND-EXOR PLA is applied to the poperation circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.5
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• pp.411-421
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• 1988

This paper offers a method to design CCD four-valued circuits using the tabular method. First, the four-valued logic function is decomposed by hand-calculation or computer program. Nest, the algorithm is derived form the tabular method based on the decomposition process to realize the DDC four-valued circuit. According to this algorithm, the two-variable four valued logic function is decomposed and realized by CCD network with four basic gates. The synthesis method in this paper proves that the number of devices and cost is considerably reduces as compared with the existing methods to realize the same logic functions.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.29-33
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• 1978

In this paper, the properties of Galois fields defined over any finite field are analysed to derive Galois switching functions and the arithmetic operation methods over any finite field are showed. The polynomial expansions over finite fields by Lagrange's interpolation method are derived and proved. The results are applied to multivalued single variable logic networks.

• Proceedings of the Korea Multimedia Society Conference
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• 2002.11b
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• pp.587-592
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• 2002

본 논문에서는 De Bruijn 그래프에 기초한 다중처리기구성의 한 가지 방법을 제안하였다. 제안한 방법에서는 유한체상의 수학적 성질과 그래프의 성질을 사용하여 변환연산자를 제한하였으며, 이들 변환연산자를 이용하여 De Bruijn 그래프의 변환표를 도출하였다. 그리고, 이 변환표로부터 유한체상의 De Bruijn 그래프를 도출하였다. 제안한 다중처리기는 유한체상의 임의의 소수와 양의 정수에 대해 구성할 수 있으며 고장허용컴퓨팅시스템, 파이프라인 시스템, 병렬처리 네트워크, 스위칭 함수와 이의 회로, 차세대 디지털논리시스템 및 컴퓨터구조 중의 하나인 다치디지털논리시스템 등에 적용할 수 있으리라 전망된다.

• Journal of Advanced Navigation Technology
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• v.16 no.1
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• pp.62-69
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• 2012

Multiple-control Toffoli(MCT) gates are macro-level multiple-valued gates needing quantum technology dependent primitive gates, and have been used in Galois Field sum-of-product (GFSOP) based synthesis of quantum logic circuit. Reversible logic is very important in quantum computing for low-power circuit design. This paper presents a reversible GF4 multiplier at first, and GF4 multiplier based quaternary MCT gate realization is also proposed. In the comparisons of MCT gate realization, we show the proposed MCT gate can reduce considerably primitive gates and delays in contrast to the composite one of the smaller MCT gates in proportion to the multiple-control input increase.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.189-194
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• 2017

The reversibility of a quantum logic circuit can be realized when two reversible conditions of information reversible and energy reversible circuits are satisfied. In this paper, we have modeled the computation cycle required to recover the information reversibility from the multivalued quantum logic to the original state. For modeling, we used a function embedding method that uses a unitary switch as an arithmetic exponentiation switch. In the quantum logic circuit, if the adjoint gate pair is symmetric, the unitary switch function shows the balance function characteristic, and it takes 1 cycle operation to recover the original information reversibility. Conversely, if it is an asymmetric structure, it takes two cycle operations by the constant function. In this paper, we show that the problem of 2-cycle restoration according to the asymmetric structure when the hybrid MCT gate is realized with the ternary M-S gate can be solved by equivalent conversion of the asymmetric gate to the gate of the symmetric structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.31-39
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• 1990

An optimization problem of AND-EXOR PLA's with input decoders can be regarded as a minimization problem of Exclusive-Or Sum-Of-Products expressions (ESOP's) for multiple-valued input two-valued output functions. In this paper, We propose a minimization algorithm for ESOP's. The algorithm is based on an iterative improvement. Five rules are used to replace a pair of products with another one. We minimized many ESOP's for arithmetic circuits. In most cases, ESOP's required fewer products than SOP's to realized same functions.