• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.481-483
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• 2008

본 논문은 다양한 종류의 전원을 구비해야 하는 다중출력 전원 시스템을 위한 영전류 스위칭 LLC 공진형 Post-regulator를 제안한다. 기존의 LLC 공진형 컨버터는 정밀한 다중 출력을 얻기 위해 추가의 DC/DC 컨버터가 구성되었고, 이는 전력 변환 효율 감소 및 제조 원가 상승의 단점을 갖고 있다. 제안된 컨버터는 각 소자의 내압 및 전류 스트레스가 작고, 요구되는 출력 당 1 개의 보조 스위치만으로 구현되므로 저가격화에 유리하다. 또한 전력이 전달되는 시점의 공진 전류의 초기값을 가변함으로서 정밀하게 제어되는 다중 출력 전압을 획득할 수 있고, 각 전압의 출력 순서 제어도 가능한 장점이 있다. 뿐만 아니라, 독립된 공진탱크를 이용하기 때문에 공진탱크 설계가 용이하며, 최근 전자 제품의 추세인 슬림화의 요구에 부응할 수 있다. 또한, 제안된 Post-regulator의 모든 전력 스위치는 ZCS가 가능하므로 스위칭 손실을 최소화 할 수 있다. 최종적으로 본 논문에서 제안한 영전류 스위칭 LLC 공진형 Post-regulator를 제작하고, 고찰된 실험결과를 제시하여 제안된 컨버터 및 전원시스템의 우수성과 이론적 분석의 타당성을 검증한다.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.238-240
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• 2008

다양한 기능을 동시에 구현하는 최근의 전자제품을 위한 전력 시스템은 다양한 종류의 전원을 구비해야 하며, 고효율 저가격 특성이 필수적이다. 이를 위해 본 논문은 단일 변압기를 이용한 중 용량급의 고효율 저가격형 다중출력 LLC 공진형 컨버터를 제안한다. 제안된 컨버터는 단일 변압기를 이용하고, 요구되는 출력 당 추가된 1 개의 보조 스위치만으로 구현되므로 저가격화에 유리하다. 또한 제안된 회로의 모든 전력 스위치들은 ZVS 및 ZCS가 가능하므로 스위칭 손실을 최소화 할 수 있다. 최종적으로 제안된 컨버터 및 전원시스템의 우수성과 이론적 분석의 타당성 검증을 위해 42" FHD급 PDP용 전원회로를 위한 시작품을 제작하여 고찰된 실험결과를 제시한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.27-36
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• 2004

In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.183-184
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• 2012

본 논문에서는 출력 인덕터 리플과 2차 측 정류기의 공진 전압을 저감할 수 있는 다중 위상천이 풀 브리지 컨버터를 제안한다. 제안된 회로는 총 8개의 스위치가 사용되며, 각 4개의 스위치가 하나의 위상천이 풀 브리지 인버터 부를 구성하는 구조이다. 기존 위상천이 풀 브리지 컨버터의 경우, 진상레그와 지상레그의 위상차이를 조절하여 출력전압을 제어하는데 반해, 제안된 회로는 진상레그와 지상레그의 위상차이 뿐만 아니라 각 풀 브리지 인버터 부의 위상차이를 동시에 조절하여 출력전압을 제어하는 것이 특징이다. 이를 통하여 제안회로는 출력 인덕터 전류 리플 및 2차 측정류기의 공진 전압을 크게 저감시킬 수 있어 고 효율화에 유리하다. 본 논문에서는 제안된 회로의 이론적 해석 및 PSIM 모의실험을 수행하며, 450W급 시작품을 제작하여 제안회로의 타당성을 검증하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.11
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• pp.1689-1700
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• 1993

WDM(Wavelength Division Multiplexing) based-on fixed wavelengths is a new means of utilizing the bandwidth of optical fibers. In this Paper, an improved virtual topology called "(a, $\beta$,${\gamma}$) ShuffleNet " is introdced for designing large-scale WDM switches. The proposed one is an architecture created by vertically stacking x planes of a ($\beta$,${\gamma}$) ShuffleNet in parallel via $\beta$r nodes called "bridge nodes" so that N-by-N(N=(x*$\beta$${\gamma}$*${\gamma}$) switching is achieved based on the self-routing algorithm for each ($\beta$,${\gamma}$) ShuffleNet. With the topological parallelism, in contrast to the conventional virtual topologies, the diameter of 2${\gamma}$ hops can be fixed and high utilization and performance are provided while N increases. Such a scalability characteristic allows to design a growable broadband switch. As for the delay, we show that the traffic locality, due to the topological feature. result in low delay characteristics.lay characteristics.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.101-108
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• 2017

As the quantum gate matrix is a $r^{n+1}{\times}r^{n+1}$ dimension when the radix is r, the number of control state vectors is n, and the number of target state vectors is one, the matrix dimension with increasing n is exponentially increasing. If the number of control state vectors is $2^n$, then the number of $2^n-1$ unit matrix operations preserves the output from the input, and only one can be performed the unitary operation to the target state vector. Therefore, this paper proposes a new method of function embedding that can replace $2^n-1$ times of unit matrix operations with deterministic contribution to matrix dimension by arithmetic power switch of the unitary gate. The proposed function embedding method uses a binary literal switch with a multivalued threshold, so that a general purpose hybrid MCU gate can be realized in a $r{\times}r$ unitary matrix.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.1910-1916
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• 1999

This paper suggested to solve ATM switch performance and service rate which was input buffer managed scheme in ATM network with burst traffic characteristics, For this purpose, ATM multiplexer is prepared before sending for handling burst random input traffic to multiplex and then sort based on cell inter-arrival time and cell processing due time which had been marked after that. The server looks for cell header with the most shortest due time and sends it, thus it is satisfied that real time traffic for instance CBR and rt-VBR was guaranteed cell processing time to send fast than non real time traffic. For analysis of ATM switch performance with cell processing due time and priority, each output port has divided into four different virtual buffer and each buffer has assigned different cell inter-arrival time and processing due time according to ATM Forum for example CBT/rt-VBR, nrt-VBR, ABR and UBR and showed it’s optimal service parameters then analyzed service rate behaviors according to each traffic characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.684-690
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• 2010

Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1610-1619
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• 1998

The ABR service class provides feedback based traffic control to transport bursty data traffic efficiently. Feedback based congestion control has first been studied to be applied to unicast connections. Recently. several congestion control algorithms for multicast connections have also been proposed as the number of ABR applications requiring multicast increases. With feedback based congestion control, the effectiveness of a traffic control scheme diminishes as propagation delay increases. Especially for a multicast connection, a remote destination may suffer unfair service compared to a local destination due to the delayed feedback. Amelioration of the disadvantages caused by feedback delay is therefore more important for remote destinations in multicast connections. This paper proposes a new switch behavior to provide effective feedback based mathc control for rentoh destinations. The proposed switches adjust the service rate dynamically in accordance woth the state of the downstream, that is, the congestion of the destinaion is immediately controlled by the nearest apstream switch before the source to ramp down the transmission rate of the connection. The proposed switch has an implementation overhead to have a separate buffer for each VC to adjust the service rate in accordance with a backward Rm cell of each VC. The buffer requirement id also increased at intermediate switches. Simulation results show that the proposed switch reduces the cell loss rate in both the local and the remote destinations and slso amelioratd the between the two destinations.