• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.791-793
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• 1999

제어 컴퓨터의 고장으로 인해 인명이나 재산에 치명적 영향을 미치는 safety-critical 실시간 시스템을 제어하고 모니터링하기 위해 디지털 컴퓨터의 사용은 점점 일반화되고 있다. 특히, VLSI 기술의 급격한 발달로 인해 하드웨어가 초소형화 되고 대량생산이 가능해진 현실에서 이러한 제어 컴퓨터의 극대화된 신뢰도 요구를 만족시키기 위해 막중한 하드웨어 여분(hardware redundancy)이 널리 사용되고 있는 실정이다. 본 논문에서는 N개의 다중 모듈(multi-module)로 이루어진 하드웨어 여분의 운영 모드를 분석하고 각 운영 모드에서 고장이 발생할 경우 모드의 전환과 그로 인한 신뢰도의 변화를 계산할 것이다. 그리고 간단한 시뮬레이션을 통해 전환된 여러 모드 중 가장 우수한 신뢰도를 갖는 모드를 평가하게 된다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.9
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• pp.1169-1174
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• 2013

Most products are indeed governed by multiple failure modes. However, there are few cases in which reliability analysis applies to only one failure mode at a time. Furthermore, reliability data do not include information about failure modes, or the reliability analysis is performed using a representative failure mode. The Weibull shape parameter for failure modes is more important than one for products in the reliability qualification test. This paper presents reliability analysis methods for a mechanical component with multiple failure modes. These methods include the competing failure modes (CFM) method and the mixed Weibull method. Pneumatic cylinder test data with three failure modes are presented to estimate the shape parameter for each separate failure mode. In addition, reliability measures (B10 life, characteristic life) of the pneumatic cylinder considering three failure modes were compared with those assuming a single failure mode.

• Proceedings of the KIPE Conference
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• 2020.08a
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• pp.282-283
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• 2020

3상 컨버터에서 스위치의 개방고장이 발생한 경우 고장 전류에 직류 및 고조파 성분이 발생할 수 있으며, 보호회로에 의한 고장 감지가 어려우므로 주변 기기에 2차 고장이 발생할 수 있다. 단일 및 이중 스위치 개방고장의 경우 21가지 고장 모드가 존재한다. 본 논문에서는 이러한 고장 모드를 진단하기 위해 정지 좌표계 d-q축 전류의 직류 및 고조파 성분을 활용하는 two-step 구조의 ANN(Artificial Neural Network)을 제안한다. 고장 시에 발생된 직류 및 고조파 성분 전류는 ADALINE(Adaptive-Linear Neuron)을 통해 얻는다. 고장 진단의 첫 번째 단계에서는 직류 성분을 기반으로 ANN을 이용하여 고장모드를 6개 영역으로 분류한다. 두 번째 단계에서는 6개의 각 영역에서 직류 성분과 전류의 THD(Total Harmonics Distortion)를 기반으로 ANN을 이용하여 개방고장이 발생한 스위치를 진단한다. 제안된 Two-step 방법으로 고장을 진단하므로써 간단한 구조로 ANN의 설계가 가능하다. 3.7kW급 3상 PWM 컨버터로 실험을 통해 제안된 방법의 효용성을 검증하였다.

• Journal of the Korean Society for Railway
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• v.20 no.3
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• pp.349-355
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• 2017

Failures of railway systems can result in train delays or accidents, and therefore high reliability is required to ensure safety of railway systems. To improve reliability, railway systems are designed with redundant systems so that the standby system will continue to function normally even if the primary system fails. Generally, overall system reliability can be evaluated by the reliabilities of the parts of the whole system and the reliability of the redundant system considering common failures in case of each system is not conform physical, functional and process independent. In this study, the reliability of the hot-standby sparing system is analyzed the independent systems and dependent systems with common failures. The reliability for the standby system can be effectively analysed using Markov models, which can model the redundant configuration and the state transition.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.38 no.2
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• pp.169-179
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• 2010

Satisfying the same probability of loss of control and essentially two fail operative performance with a triplex computer architecture requires a lot of modification of the conventional redundancy management design techniques, previously employed in quadruplex digital flight control computer. T-50 FCS for triplex redundancy management design applied an advanced digital flight control architecture with an I/O controller which is functionally independent of the digital computer to achieve the same reliability and special failure analysis and isolation schemes for fail operational goals with a triplex configuration. The analysis results indicated that the triplex flight control system is to satisfy the safety requirement utilizing the advanced flight control techniques and the system performance of the implemented flight control system was verified by failure mode effect test.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.2
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• pp.84-92
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• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of Internet of Things and Convergence
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• v.8 no.6
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• pp.55-63
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• 2022

In recent years, with the rapid development of large and medium-sized urban rail transit in China, the total operating mileage of high-speed railway and the total number of EMUs(Electric Multiple Units) are rising. The system complexity of high-speed EMU is constantly increasing, which puts forward higher requirements for the safety of equipment and the efficiency of maintenance.At present, the maintenance mode of high-speed EMU in China still adopts the post maintenance method based on planned maintenance and fault maintenance, which leads to insufficient or excessive maintenance, reduces the efficiency of equipment fault handling, and increases the maintenance cost. Based on the intelligent operation and maintenance technology of PHM(prognostics and health management). This thesis builds an integrated PHM platform of "vehicle system-communication system-ground system" by integrating multi-source heterogeneous data of different scenarios of high-speed EMU, and combines the equipment fault mechanism with artificial intelligence algorithms to build a fault prediction model for traction motors of high-speed EMU.Reliable fault prediction and accurate maintenance shall be carried out in advance to ensure safe and efficient operation of high-speed EMU.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.41 no.7
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• pp.588-595
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• 2013

Airborne SAR system is the imaging Radar system that is loaded on a manned or unmanned aircraft, which is in charge of high quality image acquisition and moving target detection. This paper describes the operational requirements for the Airborne SAR system and suggests the operational concept to satisfy the requirements. To be specific, it describes the interface with airborne system, state definition and transition, operation mode based on mission definition file, fault management, and data storing and transmission concept. Finally, it gives the ground test results to verify the SAR system operational concept.

• The Transactions of the Korea Information Processing Society
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• v.4 no.7
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• pp.1900-1906
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• 1997

In this paper, the efficient BILBO(named EBILBO) is designed for BIST that is able to batch the testing when circuit is designed on FPGA. The proposed algorithm of batch testing is able to test the normal operation speed with one-pin-count that can control all part of large and complex circuit. PRTPG is used for the test pattern and MISR is used for PSA. The proposed algorithm of batch testing is VHDL coding on behavioral description, so it is easily modified the model of test pattern generation, signature analysis and compression. The EBILBO's area and the performance of designed BIST are evaluated with ISCAS89 benchmark circuit on FPGA. In circuit with above 600 cells, it is shown that area is reduced below 30%, test pattern is flexibly generated about 500K and the fault coverage is from 88.3% to 100%. EBILBO for the proposed batch testing BIST is able to execute concurrently normal and test mode operation in real time to the number of $s+n+(2^s/2^p-1)$ clock(where, in CUT, # of PI;n, # of register, p is order # of polynomial). The proposed algorithm coded with VHDL is made of library, then it well be widely applied to DFT that satisfy the design and test field on sme time.