• Journal of the Institute of Convergence Signal Processing
• /
• v.8 no.2
• /
• pp.84-90
• /
• 2007

In this paper, the demonstration of a 130-channel optical demultiplexer based on the cascaded volume holographic gratings is presented. By serially adding the second holographic grating, which has different grating period, slant angle, and center wavelength compared to those of the first grating, the operating wavelength range of the optical demultiplexer could be expanded, and therefore, the number of channels of the holographic demultiplexer is increased by twice. As a result of the experiment, a 0.4-nm-spaced demultiplexer with the channel uniformity of 3.5 dB, the 3dB-bandwidth of 0.12nm, and the channel crosstalk of -20dB is experimentally achieved.

• Proceedings of the KIPE Conference
• /
• 2018.07a
• /
• pp.165-167
• /
• 2018

본 논문은 다권선 변압기를 이용한 능동 셀 밸런싱 회로의 에너지 전달 효율을 향상시킬 수 있는 스위칭 방식을 제안한다. 다권선 변압기를 이용한 밸런싱 회로는 셀 당 하나의 스위치가 사용되며, 하나의 변압기 권선을 두 개의 셀이 공유하는 구조를 가져 다른 능동 셀 밸런싱 회로보다 소량의 능동 소자 및 수동 소자가 사용되는 장점을 갖는다. 이 밸런싱 회로는 직렬 셀 전압의 분포에 따라 에너지를 공급하는 소스 셀과 에너지를 받는 목표 셀을 선택하여 벅-부스트 및 플라이백 방식으로 동작한다. 하지만, 플라이백 동작에서 기존의 스위칭 방식을 사용할 경우, 변압기의 커플링 계수의 영향으로 인해 밸런싱 과정 중 비-목표 셀로 전달되는 에너지가 발생하게 된다. 이는 에너지 전달 효율을 감소시켜 셀 밸런싱 과정 중 새로운 셀 불균형 현상을 초래한다. 본 논문에서는 플라이백 동작에서 변압기의 커플링 영향을 최소화하여 셀 밸런싱을 효과적으로 수행할 수 있는 스위칭 방식을 제안하였다. 제안한 스위칭 방식의 성능은 1 W급 시작품을 이용한 실험을 통하여 검증되었다.

• Information and Communications Magazine
• /
• v.19 no.10
• /
• pp.78-92
• /
• 2002

고용량 파장다중분할(WDM) 전송 시스템의 수요가 폭발적으로 증가함에 따라 기존의 erbium-doped fiber amplifiers(EDFA)가 제공하는 이득 대역을 넘어서는 대역폭의 광증폭기의 개발이 촉진되고 있다. 에르븀 이외의 새로운 회토류 첨가물을 사용한 증폭기와 광섬유 내에서의 비선형 현상인 라만 산란에 의한 라만 증폭기에 집중적인 연구가 그 예라 하겠다. 최근 몇 년간의 집중적인 연구를 통하여 현재의 광대역 광 증폭기는 기존의 EDFA(C 벤드 EDFA)가 제공하는 광이득대역의 4∼5배 정도를 쉽게 제공할 수 있다. 이러한 목적을 가지고 통신시장에서 사용될 수 있는 1500nm 근처 대역의 증폭에 대한 세가지의 증폭 기술이 연구되고 있다. 우선, S+밴드(1450-1480nm)와 S밴드(1480-1530nm)의 증폭을 위한 thulium-doped fluoride fiber amplifiers(TDFFA), C 밴드(1530-1560nm)와 L 밴드(1570-1610nm)를 위한 EDFA, 그리고 마지막으로 100nm 이상의 이득대역과 S+에서 L밴드까지 증폭파장대역의 선택이 자유로운 라만 증폭기가 있다. 또한 위의 세 기술을 직렬 또는 병렬로 조합하여 사용하는 증폭기가 있다. 이러한 증폭기 모두에 대해서 실험적인 보고는 많이 있었으나, 내부의 에너지 준위가 복잡하여 증폭 기제가 복잡하고, 실험 파라미터를 측정하기가 어려워서 광대역증폭기의 성능을 예측하기 어려운 점이 있었다. 게다가 이러한 상황에서 광대역증폭기에 대한 해석적이거나 수치해석적인 심도깊은 연구가 부족하여 앞으로 증폭기를 다양하게 응용하기 위한 성능의 예측이 어려울 것으로 보인다. 이는 광대역 증폭기 기반의 전송 시스템을 성공적으로 적용하는데 제한을 줄 것이다. 따라서 본 논문에서는 광대역 증폭기(C/L밴드 EDFA, 라만 증폭기, TDFA)에 대한 실험적인 분석뿐만 아니라 해석적, 수치해석적인 분석 방법까지 그 응용의 예와 함께 소개할 것이다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.1A
• /
• pp.44-49
• /
• 2008

Recently, a so called orthogonal spatial multiplexing(OSM) scheme was presented which allows simple maximum likelihood decoding at the receiver with single phase feedback In this paper, by serially concatenating this scheme by a linear precoder, a new closed-loop SM scheme is proposed for two transmit arid two receive antennas. By computer simulation results, we show that the proposed scheme outperforms the conventional SM and OSM. For the proposed code, we also propose a new simple decoding algorithm which leads to a greatly reduced decoding complexity compared with the ML receiver without any loss of error performance.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.7B
• /
• pp.892-896
• /
• 2011

This paper proposes a two-stage synchronization scheme using a serial search non-coherent correlator appropriate for the IEEE 802.15.4a system. The proposed method improved the synchronization performance by using multi-pulse signals unlike the conventional method using single-pulse signals. It also compensated for the degradation of performance at low SNR resulting from the use of fixed threshold by applying the adaptive threshold technique. The proposed method showed a detection probability that is higher by approximately 0.2-0.3 compared with the conventional method in the IEEE 802.15.4a channel model.

• Journal of the Korea Society of Computer and Information
• /
• v.6 no.4
• /
• pp.12-20
• /
• 2001

The problem of software bottle-neck may be arised from unbalance of demands and supply of software. This is caused from the fact that the capability of programmer could not be improved in software development. Therefor, the new method of software development should aim at improving the productivity of software. This paper presents the expressions to be the standardized software Program modules by means of the software chip. The expressions are consist of name, input, output, and iteration of each software chip. And they simple express a combination and separation in sequence, parallel, iteration, composition, mixing, and variety form. Therefore they can easily software reuse as a result of analyzing the flow of data clearly.

• Journal of Korea Multimedia Society
• /
• v.3 no.5
• /
• pp.526-534
• /
• 2000

There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.2
• /
• pp.14-25
• /
• 1999

The IEEE standard 1149.1, which was proposed to increase the observability and the controllability in I/O pins, makes it possible the board level testing. In the boundary-scan environments, many shift operations are required due to their serial nature. This increases the test application time and the test application costs. To reduce the test application time, the method based on the parallel opereational multiple scan paths was proposed, but this requires the additional I/O pins and the internal wires. Moreover, it is difficult to make the designs in conformity to the IEEE standard 1149.1 since the standard does not support the parallel operation of data shifts on the scan paths. In this paper, the multiple scan path access algorithm which controls two scan paths simultaneously with one test bus is proposed. Based on the new algorithm, the new algorithm, the new board level BIST architecture which has a relatively small area overhead is developed. The new BIST architecture can reduce the test application time since it can shift the test patterns and the test responses of two scan paths at a time. In addition, it can reduce the costs for the test pattern generation and the test response analysis.

• Journal of Korean Elementary Science Education
• /
• v.23 no.4
• /
• pp.344-356
• /
• 2004

In this study, we developed the program for 'Discretionary Activity' focusing on the multiple activities with everyday-life materials to enhance scientific creativity (MAEM-SC), which was specifically for students in the 6-7th grade according to the 7th curriculum in Korea. As important factors for scientific creativity, we selected the ability to find out the context relevant to scientific problems, the ability to connect the problem context to scientific knowledge, the ability to invent the ways to solve the problem scientifically, and ability to concentrate on the scientific problem solving activity. The topics of the program were drawn from common and familiar things in our everyday contexts, such as human body, everyday tools, food, play and toys, and everyday episodes. The multiple activities here mean the activities which are systematically constructed with the various types of activities with a specific intention. The multiple activities were designed in three types, that is, series type, parallel type, and combination type. Each of them consists of the several activities as follows: estimating and measuring, carrying out an experiment using body, inventing implement (tools), thinking statistically, writing creatively with scientific themes, and connecting one concept to another concept etc. Through a trial of the program, we found that this program has some positive influence on the enhancement both of the ability to find out the context relevant to scientific problems and the ability to connect it to the students' existing scientific knowledge.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11C
• /
• pp.1077-1087
• /
• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.