• Korean Journal of Food Science and Technology
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• v.32 no.2
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• pp.356-362
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• 2000

Yakju(rice wine) was sterilized with high-voltage square-wave pulses of $1\;{\mu}s$ duration at various electric field strengths and frequencies on a serial multiple electrode pulsed electric field(PEF) treatment system consisted of 7 electrodes connected in series. The initial microbial counts of Yakju were $1.88{\times}10^3{\sim}2.13{\times}10^4$ CFU/mL for total aerobes, $1.55{\times}10^3{\sim}2.85{\times}10^4$ CFU/mL for lactic acid bacteria and $1.72{\times}10^3{\sim}2.39{\times}10^4$ CFU/mL for yeasts. The sterilization of microorganisms in Yakju was a first order reaction and the sterilization effect increased as the field strength and the frequency increased. The $D_{Hz}-value$ and the $D_{PEF}-value$ decreased with the electric field strength. Yeast showed lower $D_{PEF}-value$ than bacteria. Lactic acid bacteria showed lower $D_{PEF}-value$ than general aerobic bacteria under the electric field strength below 30 kV/cm, but higher ones under that above 40 kV/cm. The $Z_{PEF}-value$ of general aerobic bacteria, lactic acid bacteria and yeast in Yakju were 39.4, 49.3 and 47.6 kV/cm, respectively. The PEF sterilization resulted in less changes in color and sensory properties than heat sterilization, and the PEF treated Yakju showed superior quality to the heat treated one. The commercial sterilization of Yakju was accomplished with 2-cycle treatment on the tested serial PEF treatment system.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.4
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• pp.47-51
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• 2003

Due to the asymptotic property, deadbeat control which is well used in digital control system can not be applied to the continuous time system. But recently by use of the finite Laplace Transform to transfer function and establishment of some settling conditions, CDBC(Continuous time Deadbeat Control) is studied. For CDBC design, transfer function is constituted with delay elements and then order and interpolation conditions are derived. In other way, digital deadbeat controller is implemented and it's output is changed to continuous type by smoothing elements. In this paper multirate sampling is used and so inner controller is sampled faster than output feedback loop. And End order smoothing elements is placed to the output of digital deadbeat controller. By the multirate sampling overall output response is improved. The controller is impleneted as a serial integral compensator in the forward path and a local feedback compensator introduced into the outpute feedback loop. Matlab Simulink is used for simulation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.6
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• pp.78-85
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• 2009

In time-varying multipath fading channels, orthogonal frequency division multiple access (OFDMA) uplink systems suffer severe performance degradation caused by inter-channel interference (ICI). In this paper, we propose a hybrid interference cancellation (HIC) for suppressing the degradation effect of ICI. The proposed HIC can achieve both exact interference cancellation and low detection complexity through efficient combination of parallel detection and serial cancellation. Simulation results show that, as the effect of Doppler increases, the proposed HIC achieves bit error rate (BER) performance enhancement in compared with severe performance degradation of conventional OFDMA receivers. In addition, both the computational complexity and total detection time are reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.7-14
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• 2009

Lately, NAND flash cards have been used to store massive amounts of multimedia data. However, these nand flash cells itself has a slow operation time and by that, the nand flash cards are not appropriate for high performance massive data transfer. Indeed, most flash card products have a disadvantage in that they require plenty of time to transfer massive amounts of data. Therefore, we propose a new architectural design for the hardware and software of the NAND flash cards by improving their data transfer rate. Our design is based on a multiprocessing which is different from the conventional serial processing method. We simulated our design under the VIP (Virtual IP) environment, and verified our work using FPGA test platforms. As a result, the downloading performances was approximately 160MB/s on VIP and 85.3MB/s on FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.36-42
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• 2008

40Gb/s CMOS Clock and Data Recovery circuit design for optical serial link is proposed. The circuit generates 8 multiphase clock using LC tank PLL and controls the phase between the clock and the data using the $2{\times}$ oversampling Bang-Bang PD. 40Gb/s input data is 1:4 demultiplexed and recovered to 4 channel 10Gb/s outputs. The design was progressed to separate the analog power and the digital power. The area of the chip is $2.8{\times}2.4mm^2$ for the inductors and the power dissipation is about 200mW. The chip has been fabricated using 0.18um CMOS process. The measured results show that the chip recovers the data up to 9.5Gb/s per channel(Equivalent to serial input rate of up to 38Gb/s).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.1 s.343
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• pp.95-102
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• 2006

In this paper, we present the performance analysis and design of a multi-path searcher operating over Rayleigh fading channels when multiple transmit antennas are employed in the down-link of W-CDMA system. The simulation results for the receiver operating characteristics (ROC) for 1, 2, and 4 transmit antennas are presented to corroborate the theoretical analyses. We also propose a procedure to find the optimum parameters of double-dwell serial searcher according to the number of the multiple transmit antennas. Our analyses and simulations indicate that post-detection integration is not necessary when the number of transmit antennas is more than two. Finally, we found that increasing transmit diversity order does not necessarily improve the detection performance when the received pilot signal strength is relatively low. Therefore, this gives us a practical criterion on increasing transmit diversity order.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.323-323
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• 2014

기존의 태양전지 기술은 기술 장벽이 매우 낮고 대량 생산을 통한 단가 절감하는 구조를 가지고 있어 대규모 자본을 가진 후발 기업에게 잠식되기 쉽다. 그러나, III-V족 화합물 반도체를 이용한 집광형 고효율 태양전지는 기술 장벽이 매우 높은 기술 집약 산업이므로 독자적인 기술을 확보하게 되면 독점적인 시장을 확보 할 수 있어 미래 고부가 가치 산업으로 적합하다. 특히 III-V족 화합물 반도체 태양전지는 III족 원소(In, Ga, Al)와 V족 원소(As, P)의 조합으로 0.3 eV~2.5 eV까지 밴드갭을 가지는 다양한 박막 제조가 가능하여 다양한 흡수 대역을 가지는 태양전지 제조가 가능하기 때문에 다중 접합 태양전지 제작이 가능하다. 또한 III-V 화합물 반도체는 고온 특성이 우수하여 온도 안정성 및 신뢰성이 우수하고, 또한 집광 시 효율이 상승하는 특성이 있어 고배율 집광형 태양광 발전 시스템에 가장 적합하다. Si 태양전지의 경우 100배 이하의 집광에서 사용하나, III-V 화합물 반도체 태양전지의 경우 500~1000배 정도의 고집광이 가능하다. 이러한 특성으로 III-V 화합물 반도체 태양전지 모듈 가격을 낮출 수 있고, 따라서 Si 태양전지 시스템과 비교하여 발전 단가 면에서 경쟁력을 확보할 수 있다. III-V 화합물 반도체는 다양한 밴드갭 에너지를 가지는 박막 제조가 용이하고, 직접천이(direct bandgap) 구조를 가지고 있어 실리콘에 비해 광 흡수율이 높다. 또한 터널정션(tunnel junction)을 이용하면 광학적 손실과 전기적 소실을 최소화 하면서 다양한 밴드갭을 가지는 태양전지를 직렬 연결이 가능하여 한 번의 박막 증착 공정으로 넓은 흡수대역을 가지며 효율이 높은 다중접합 태양전지 제작이 가능하다. 이에 걸맞게 본연구에서는 화학기상증착장치(MOCVD)를 이용하여 InAsP 나노선을 코어 쉘 구조로 성장하여 태양전지를 제작하였다. P-type Dopant로는 Disilane (Si2H6)을 전구체로 사용하였다. 또한 Benzocyclobutene (BCB) 폴리머를 이용하여 Dielectric을 형성하였고 Sputtering 방법으로 증착한 ZnO을 투명 전극으로 사용하여 나노선 끝부분과 실리콘 기판에 메탈 전극을 형성하였다. 이를 통해 제작한 태양전지는 솔라시뮬레이터로 측정했을때 최고 7%에 달하는 변환효율을 나타내었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.12A
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• pp.1311-1319
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• 2007

This paper presents the VHDL implementation procedure of the passive RFID tag operating in Ultra High Frequency. The operation of the tag compatible with the EPCglobal Class1 Generation2(GEN2) protocol is verified by timing simulation after synthesis and implementation. Due to the reading range with relatively large distance, a passive tag needs digital processor which facilitates faster decoding, encoding and state transition for enhancement of an interrogation rate. In order to satisfy linking time, the pipe-line structure is used, which can minimize latency to serial input data stream. We also propose the sampling strategy to decode the Preamble, the Frame-sync and PIE symbols in reader commands. The simulation results with the fastest data rate and multi tags environment scenario show that the VHDL implemented tag performs faster operation than GEN2 proposed.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.7 s.361
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• pp.7-11
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• 2007

This paper presents a multiband octa-phase LC VCO for SDR receiver. Four identical LC VCOs are connected by using series coupling transistor to obtain the octa-phase signal and low phase noise characteristic. For a multiband application, a band tuning circuit that consists of a switch capacitor circuit and two MOS varactors is proposed. As the MOS switch is on/off state, the frequency range will be varied. In addition, two varactors make the VCO be immune to process variation of the oscillation frequency. The VCO is designed in 0.18-um CMOS technology, consumes 12mA current from 1.8V supply voltage and operates with a frequency band from 885MHz to 1.342GHz (41% tuning range). As driving sub-harmonic mixer, the proposed VCO covers 3 standards(CDMA 2000 1x, WCDMA, WiBro). The measured phase noise is -105dBc@100kHz, -115dBc@1MHz, -130dBc@10MHz for CDMA 2000 1x, WCDMA, WiBro respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.13 no.3
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• pp.110-116
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• 2008

In this paper, we proposed an improvement technique of image encryption using binary phase computer generated hologram(BPCGH) and multi exclusive-OR(XOR) operations. For the encryption process, a BPCGH that reconstructs the original image is designed, using an iterative algorithm, and the resulting hologram is regarded as the image to be encrypted. The BPCGH is encrypted through the exclusive-OR operation with the random generated phase key image. Then the encrypted image is divided into several slide images using XOR operations. So, the performance of encryption for the image is improved. For the decryption process, we cascade the encrypted slide images and phase key image and interfere with reference wave. Then decrypted hologram image is transformed into phase information. Finally, the original image is recovered by an inverse Fourier transformation of the phase information. If the slide images are changed, we can get various decrypted BPCGH images. In the proposed security system, without a random generated key image, the original image can not be recovered. And we recover another hologram pattern according to the slide images, so it can be used in the differentiated authorization system.