• Title/Summary/Keyword: 다이 레이아웃

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A Study on Progressive Die Design by the using of Finite Element Method (유한요소법을 이용한 프로그레시브 금형 설계에 관한 연구)

  • Park, Chul-Woo;Kim, Young-Min;Kim, Chul;Kim, Young-Ho;Choi, Jae-Chan
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2002.05a
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    • pp.1012-1016
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    • 2002
  • This paper describes a research work of developing computer-aided design of a product with bending and piercing for progressive working. An approach to the system for progressive working is based on the knowledge-based rules. Knowledge for the system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. The system has been written in Auto-LISP on the Auto-CAD with a personal computer and is composed of four main modules, which are input and shape treatment, flat pattern layout, strip layout, and die layout modules. The system is designed by considering several factors, such as bending sequences by fuzzy set theory, complexities of blank geometry, punch profiles, and the availability of a press equipment. Strip layout drawing generated in the strip layout module is presented in 3-D graphic forms, including bending sequences and piercing processes with punch profiles divided into for external area. The die layout module carries out die design for each process obtained from the results of the strip layout. Results obtained using the modules enable the manufacturer for progressive working of electric products to be more efficient in this field.

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A Study for Process Planning of Progressive Working by the using of Fuzzy Set Theory (Fuzzy set 이론을 이용한 프로그레시브 가공의 공정설계에 관한 연구)

  • Kim, Y. M.;Kim, J. H.;Kim, C.;Choi, J. C.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2001.04a
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    • pp.735-739
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    • 2001
  • This paper describes a research work of developing computer-aided design of a product with bending and piercing for progressive working. An approach to the system for progressive working os based on the knowledge-based rules. Knowledge for the system is formulated from plasticity theorise, experimental results and the empirical knowledge of field experts. the system has been written in AutoLISP on the AutoCAD with a personal computer and is composed of three main modules, which are input and shape treatment, flat pattern layout and strip layout modules. Strip layout of the system is designed by using fuzzy set theory. Process planning is determinated by fuzzy value according to several rules. Strip layout drawing generated in strip layout module is presented in 3-D graphic forms, including bending sequences and piercing processes with punch profiles divided into for external area. Results obtained using the modules enable the manufacturer for progressive working of electric products to be more efficient in this field.

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Development of an Automated Progressive Design System for Manufacturing Product with Multi Processes, Piercing, Bending, and Deep Drawing (복합공정(피어싱, 벤딩, 디프드로잉)을 갖는 제품 제조를 위한 프로그레시브 설계 자동화 시스템 개발)

  • Hwang, Beom-Cheol;Kim, Chul;Bae, Won-Byong
    • Journal of the Korean Society for Precision Engineering
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    • v.25 no.12
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    • pp.55-64
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    • 2008
  • This paper describes a research work of developing an automated progressive design system for manufacturing the product with multi processes such as piercing, bending, and deep drawing. An approach to the system for progressive working is based on the knowledge-based rules. Knowledge for the system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. The system consists of three main modules, which are shape treatment, strip layout, and die layout modules. Based on knowledge-based rules, the system is designed considering several factors, such as material and thickness of a product, piercing, bending and deep drawing sequence, and the complexities of the blank geometry and punch profiles. It generates the strip layout drawing for an automobile product. Die design for each process is carried out through the die layout module from the results of the strip layout module. Results obtained using the modules enable the designers for manufacturing products with multi processes to be more efficient in this field.

A Study on the Development of Computer Aided Die Design System for Lead Frame, Semiconductor (반도체 리드 프레임의 금형설계 자동화 시스템 개발에 관한 연구)

  • Choe, Jae-Chan;Kim, Byeong-Min;Kim, Cheol;Kim, Jae-Hun;Kim, Chang-Bong
    • Journal of the Korean Society for Precision Engineering
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    • v.16 no.6
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    • pp.123-132
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    • 1999
  • This paper describes a research work of developing computer-aided design of lead frame, semiconductor, with blanking operation which is very precise for progressive working. Approach to the system is based on the knowledge-based rules. Knowledge for the system is formulated from pasticity theories, experimental results and the empirical knowledge of field experts. This system has been written in AutoLISP on the AutoCAD using a personal computer and in I-DEAS Drafting Programming Language on the I-DEAS Master Series Drafting with Workstation, HP9000/715(64). Transference of data between AutoCAD and I-DEAS Master Series Drafting is accomplished by DXF(drawing exchange format) and IGES(initial graphics exchange specification) methods. This system is composed of five modules, which are input and shape treatment, production feasibility check, strip-layout, data-conversion and die-layout modules. The process planning and Die design system is designed by considering several factors, such as complexities of blank geometry, punch profiles, and the availability of a press equipment and standard parts. This system provides its efficiecy for strip-layout, and die design for lead frame, semiconductor.

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An integrated CAD system for blanking or piercing of irregular-shaped sheet metal products (불규칙형상의 박판제품에 관한 블랭킹 및 피어싱용 통합적 CAD시스템)

  • Choi, Jae-Chan;Kim, Byung-Min;Kim, Chul;Yoon, J.H.
    • Journal of the Korean Society for Precision Engineering
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    • v.15 no.2
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    • pp.124-133
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    • 1998
  • This paper describes a research work of developing a computer-aided design of blanking and piercing for irregular-shaped sheet metal products. An approach to the development of compact and practical CAB system is based on the knowledge-based rules. Knowledge for the CAD system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. The system has been written in AutoLISP on the AutoCAD with a personal computer. Based on knowledge-based rules, the system, STRT-DES, is designed by considering several factors, such as complexities of blank geometry and punch profile, availability of press equipment and standard parts, utilization ratio which minimizes the scrap in a single or a pairwise operation, bridge width, grain orientation and design requirements which maximize the strength of the part when subsequent bending is involved. This system checks a forming feasibility with both internal and external features, a dimension of blanked hole, and a corner and a fillet radius for irregualrly shaped sheet metal products. Therefore this system can carry out a die design for each process which is obtained from results of an automated blank layout drawing with a best utilization ratio for irregular shape of product that was successful in production feasibility check module and those of an automated strip layout drawing and generate part drawings and the assembly drawing of die set in graphic forms.

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Development of Progressive Die CAD/CAM System for Manufacturing Lead Frame, Semiconductor (반도체 리드 프레임 제조를 위한 프로그레시브 금형의 CAD/CAM 시스템 개발)

  • Choi, J.-C.;Kim, B.-M.;Kim, C.;Kim, J.-H.;Kim, C.-B.
    • Journal of the Korean Society for Precision Engineering
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    • v.16 no.12
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    • pp.230-238
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    • 1999
  • This paper describes a research work of developing computer-aided design of lead frame, semiconductor, with blanking operation which is very precise for progressive working. Approach to the system is based on the knowledge-based rules. Knowledge for the system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. This system has been written in AutoLISP on the AutoCAD using a personal computer and in I-DEAS Drafting Programming Language on the I-DEAS Master Series Drafting with Workstation, HP9000/715(64) and tool kit on the ESPRIT. Transference of data among AutoCAD, I-DEAS Master Series Drafting, and ESPRIT is accomplished by DXF(drawing exchange format) and IGES(initial graphics exchange specification) methods. This system is composed of six modules, which are input and shape treatment, production feasibility check, strip-layout, die-layout, modelling, and post-processor modules. The system can design process planning and Die design considering several factors and generate NC data automatically according to drawings of die-layout module. As forming process of high precision product and die design system using 2-D geometry recognition are integrated with technology of process planning, die design, and CAE analysis, standardization of die part in die design and process planning of high pression product for semiconductor lead frame is possible to set. Results carried out in each module will provide efficiencies to the designer and the manufacturer of lead frame, semiconductor.

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A Study on Progressive Working of Electric Product by the using of Fuzzy Set Theory (퍼지 셋 이론을 이용한 전기제품의 프로그레시브 가공에 관한 연구)

  • Kim, J. H;Kim, Y. M.;Kim, Chul;Choi, J. C.
    • Journal of the Korean Society for Precision Engineering
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    • v.19 no.1
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    • pp.79-92
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    • 2002
  • This paper describes a research work of developing computer-aided design of a product with bending and piercing for progressive working. An approach to the system for progressive working is based on the knowledge-based rules. Knowledge for the system is formulated from plasticity theories, experimental results and the empirical knowledge of field experts. The system has been written in AutoLISP on the AutoCAD with a personal computer and is composed of four main modules, which are input and shape treatment, flat pattern layout, strip layout and die layout modules. The system is designed by considering several factors, such as bending sequences by fuzzy set theory, complexities of blank geometry, punch profiles, and the availability of a press equipment. Strip layout drawing generated in the strip layout module is presented in 3-D graphic farms, including bending sequences and piercing processes with punch profiles divided into for external area. The die layout module carries out die design for each process obtained from the results of the strip layout. Results obtained using the modules enable the manufacturer for progressive working of electric products to be more efficient in this field.

A design on low-power and small-area EEPROM for UHF RFID tag chips (UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계)

  • Baek, Seung-Myun;Lee, Jae-Hyung;Song, Sung-Young;Kim, Jong-Hee;Park, Mu-Hun;Ha, Pan-Bong;Kim, Young-Hee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.12
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    • pp.2366-2373
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    • 2007
  • In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

A CMOS RF Power Detector Using an AGC Loop (자동 이득제어 루프를 이용한 CMOS RF 전력 검출기)

  • Lee, Dongyeol;Kim, Jongsun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.51 no.11
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    • pp.101-106
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    • 2014
  • This paper presents a wide dynamic range radio-frequency (RF) root-mean-square (RMS) power detector using an automatic gain control (AGC) loop. The AGC loop consists of a variable gain amplifier (VGA), RMS conversion block and gain control block. The VGA exploits dB-linear gain characteristic of the cascade VGA. The proposed circuit utilizes full-wave squaring and generates a DC voltage proportional to the RMS of an input RF signal. The proposed RMS power detector operates from 500MHz to 5GHz. The detecting input signal range is from 0 dBm to -70 dBm or more with a conversion gain of -4.53 mV/dBm. The proposed RMS power detector is designed in a 65-nm 1.2-V CMOS process, and dissipates a power of 5 mW. The total active area is $0.0097mm^2$.

Design of PMOS-Diode Type eFuse OTP Memory IP (PMOS-다이오드 형태의 eFuse OTP IP 설계)

  • Kim, Young-Hee;Jin, Hongzhou;Ha, Yoon-Gyu;Ha, Pan-Bong
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.13 no.1
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    • pp.64-71
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    • 2020
  • eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.