• Journal of Korean Library and Information Science Society
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• v.44 no.1
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• pp.385-408
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• 2013

The purpose of this study is to build the tax ontology which can be used to manage imposables by the state or local governments. In this, the tax and related concepts were analyzed and then concept hierarchy i.e., taxonomies were formed. Especially, in the concept hierarchy, after multiple inherits were decomposed as 'primitive concepts' and then Rector's 'methodology of ontology implementation normalization', in which defined concepts were recombined, was used. The methodology employed was that the tax system, which was entangled with the direct taxes, local taxes, and property taxes that has multiple-inherits, was expressed explicitly and logically. After that, automatic classification was carried out through the inference engine, consistency was verified. Finally, some practical cases of ontology created were enumerated.

• Journal of Internet Computing and Services
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• v.11 no.2
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• pp.99-107
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• 2010

In this paper a blind watermarking algorithm for digital image is presented. The proposed method operates in wavelet domain. The watermark is decomposed into 2D-IMFs using BEMD which is the 2-dimensional extension of 1 dimensional empirical mode decomposition. The CDMA based on SS technique is applied to watermark embedding and detection process. In the watermark embedding process, each IMF of watermark is embedded into middle frequency subimages in wavelet domain, so subimages just include partial information about embedded watermark. By characteristics of BEMD, when the partial information of watermark is synthesized, the original watermark is reconstructed. The experimental results show that the proposed watermarking algorithm is imperceptible and moreover is robust against JPEG compression, common image processing distortions.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.567-572
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• 2019

In this paper, we propose an algorithm to perform convolution, pooling, and ReLU operations in CNN using binary image and binary kernel. It decomposes 256 gray-scale images into 8 bit planes and uses a binary kernel consisting of -1 and 1. The convolution operation of binary image and binary kernel is performed by addition and subtraction. Logically, it is a binary operation algorithm using the XNOR and comparator. ReLU and pooling operations are performed by using XNOR and OR logic operations, respectively. Through the experiments to verify the usefulness of the proposed algorithm, We confirm that the CNN operation can be performed by converting it to binary logic operation. It is an algorithm that can implement deep running even in a system with weak computing power. It can be applied to a variety of embedded systems such as smart phones, intelligent CCTV, IoT system, and autonomous car.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5B
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• pp.429-436
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• 2011

The G-PON is an efficient solution to implement the FTTH and have GEM frame to accomodate various protocols like Ethernet frames, IP packets, and TDM signals. Above all, the Ethernet is one of the most widely used 2nd layer protocol in the campus, the subscriber access, and the carrier service. So G-PON system has to provide an Ethernet interface with top priority. In this paper, we implement a gigabit Ethernet adapter based on Ethernet over GEM in the ITU-T G.984.3 to accommodate Ethernet protocol in the G-PON TC chip. The adapter maps each Ethernet frame to a single or multiple GEM frames and has several functions including generation of the GEM header, encapsulation of frames and the SAR. In particular, the adapter have converter (LUT) MAC address to port-ID which is a key to identify logical connections though it is not defined in specification but important. We implement the adapter with a FPGA and verify the functions of segmentation and reassembling, MAC address learning, and throughput with the logic analyzer and the Ethernet analyzer.

• The Journal of the Korea Contents Association
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• v.9 no.1
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• pp.81-88
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• 2009

In the previous work, we presented HDTS for locating logical errors in Java programs. The HDTS locates an erroneous method at an execution tree using an algorithmic program debugging technique and locates a statement with errors in the erroneous method using a step-wise program debugging. The technique can remove the unnecessary statements and nodes in debugging using a program slicing technique at the execution tree. So HDTS reduces the number of program debugging. In this paper, we design HDTS system for debugging java programs. We define small subset of Java language and design the translator that translates java source codes and the virtual machine that runs java programs. We design GUI(Graphical User Interface) for debugging.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• School Mathematics
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• v.5 no.4
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• pp.521-540
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• 2003

The processes of mathematics development and the results of it are always those of making a conquest of the circumscription by historical inevitability within the historical circumscription. It is in this article that I try to show this processes through the history of calculus. This article develops on the basis of the dialectical materialism. It views the change and development as the facts that take place not by individual subjective judgments but by social-historical material conditions as the first conditions. The dialectical materialism is appropriate for explaining calculus treated in full-scale during the 17th century, passing over ahistorical vacuum after Archimedes about B.C. 4th century. It is also appropriate for explaining such facts as frequent simultaneous discoveries observed in the process of the development of calculus. 1 try to show that mathematics is social-historical products, neither the development of the logically formal symbols nor the invention by subjectivity. By this, I hope to furnish philosophical bases on the discussion that mathematics teaching-learning must start from the real world.

• Nuclear Engineering and Technology
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• v.26 no.1
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• pp.9-18
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• 1994

The engineered safeguards of Wolsung nuclear power plant unit 1 contain redundant systems of 2-out-of-3 logic which are not operating under normal conditions but are called upon to act when emergency conditions develop. To ensure their operability, the systems are periodically tested. In this work, we develop the unavailability formulae for 2-out-of-3 logic configurations which take into account the failure probability of the channels tested due to human error in the simultaneous testing scheme. We also develop the model for the probability that the reactor is tripped during the surveillance test due to either system failure or human error. We determined the optimal inspection periods of safety systems, taking into account both the unavailability of the safety system and the probability that the reactor is tripped during the surveillance test. We compared the results with the inspection periods currently used at Wolsung NPP Unit 1. As a result, the inspection periods obtained using a minimum human error (8.24 $\times$ 1$^{-6}$ ) are shorter than those currently used in Wolsung NPP unit 1 whereas the inspection periods obtained using a maximum human error are (4.44 $\times$ 10$^{-4}$ ) longer than those used in Wolsung NPP unit 1.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.2
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• pp.59-67
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• 2003

This paper addresses how model checking methods can be applied to utilization analysis of system. Measuring a system performance using simulation is an easy task but finding the bottleneck in a certain system is not an easy task. Especially, system is getting complicated and interacts with other systems, which makes the analysis very difficult. As an alternative approach, we show that can specify system utilization properties using temporal logic, and can find a reason of a system performance drop easily using model checking.

• Proceedings of the Korea Information Processing Society Conference
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• 2018.05a
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• pp.377-380
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• 2018

인간의 추론 능력이란 문제에 주어진 조건을 보고 문제 해결에 필요한 것이 무엇인지를 논리적으로 생각해 보는 것으로 문제 상황 속에서 일정한 규칙이나 성질을 발견하고 이를 수학적인 방법으로 법칙을 찾아내거나 해결하는 능력을 말한다. 이러한 인간인지 능력과 유사한 인공지능 시스템을 개발하는데 있어서 핵심적 도전은 비구조적 데이터(unstructured data)로부터 그 개체들(object)과 그들간의 관계(relation)에 대해 추론하는 능력을 부여하는 것이라고 할 수 있다. 지금까지 딥러닝(deep learning) 방법은 구조화 되지 않은 데이터로부터 문제를 해결하는 엄청난 진보를 가져왔지만, 명시적으로 개체간의 관계를 고려하지 않고 이를 수행해왔다. 최근 발표된 구조화되지 않은 데이터로부터 복잡한 관계 추론을 수행하는 심층신경망(deep neural networks)은 관계추론(relational reasoning)의 시도를 이해하는데 기대할 만한 접근법을 보여주고 있다. 그 첫 번째는 관계추론을 위한 간단한 신경망 모듈(A simple neural network module for relational reasoning) 인 RN(Relation Networks)이고, 두 번째는 시각적 관찰을 기반으로 실제대상의 미래 상태를 예측하는 범용 목적의 VIN(Visual Interaction Networks)이다. 관계 추론을 수행하는 이들 심층신경망(deep neural networks)은 세상을 객체(objects)와 그들의 관계(their relations)라는 체계로 분해하고, 신경망(neural networks)이 피상적으로는 매우 달라 보이지만 근본적으로는 공통관계를 갖는 장면들에 대하여 객체와 관계라는 새로운 결합(combinations)을 일반화할 수 있는 강력한 추론 능력(powerful ability to reason)을 보유할 수 있다는 것을 보여주고 있다. 본 논문에서는 관계 추론을 수행하는 심층신경망(deep neural networks) 중에서 Sort-of-CLEVR 데이터 셋(dataset)을 사용하여 RN(Relation Networks)의 성능을 재현 및 관찰해 보았으며, 더 나아가 파라미터(parameters) 튜닝을 통하여 RN(Relation Networks) 모델의 성능 개선방법을 제시하여 보았다.