• Smart Media Journal
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• v.7 no.1
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• pp.37-44
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• 2018

Utilizing sequence control and numerical computing, embedded devices are used in a variety of automated systems, including those at industrial sites, in accordance with their control program. Since embedded devices are used as a control system in corporate industrial complexes, nuclear power plants and public transport infrastructure nowadays, deliberate attacks on them can cause significant economic and social damages. Most attacks aimed at embedded devices are data-coded, code-modulated, and control-programmed. The control programs for industry-automated embedded devices are designed to represent circuit structures, unlike common programming languages, and most industrial automation control programs are designed with a graphical language, LAD, which is difficult to process static analysis. Because of these characteristics, the vulnerability analysis and security related studies for industry automation control programs have only progressed up to the formal verification, real-time monitoring levels. Furthermore, the static analysis of industrial automation control programs, which can detect vulnerabilities in advance and prepare for attacks, stays poorly researched. Therefore, this study suggests a method to present a discussion on an industry automation control program designed to represent the circuit structure to increase the efficiency of static analysis of embedded industrial automation programs. It also proposes a medium term translation technology exploiting LLVM IR to comprehensively analyze the industrial automation control programs of various manufacturers. By using LLVM IR, it is possible to perform integrated analysis on dynamic analysis. In this study, a prototype program that converts to a logical expression type of medium language was developed with regards to the S company's control program in order to verify our method.

• Journal of The Korean Association For Science Education
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• v.24 no.5
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• pp.987-995
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• 2004

The purpose of this study was to analyze characteristics of problem solving process with proportional or compensational reasoning of the elementary school students. For this study, 85th grade students were selected and tested with Science Reasoning Task, information processing ability test and proportional and compensational reasoning tasks. This study revealed that students in mid concrete stage could solve the proportionality task and easy compensation task. But, most of the students could not solve difficult compensation task. And as the students got higher score in information processing test, it took them less time to solve the problem. The types of strategy used in solving proportional and compensational problem were categorized as the factor of change, building-up and the cross-product. Most of the students failed in problem solving used incorrect schema knowledge, procedure knowledge and strategy knowledge. Many students tended to use proportionality strategy to solve the difficult compensation task. Result of this study suggested that various task included different structure and the same schema knowledge can be effective for the advancement of students' proportional and compensational reasoning ability.

• Journal of Industrial Convergence
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• v.21 no.2
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• pp.125-131
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• 2023

In this paper, research was conducted to solve the problem of reducing the dimming level and flicker that occurs in the visible light communication system. Visible light communication is a convergence technology that provides both communication and lighting, and must satisfy not only communication performance but also lighting performance. However, since the existing data transmission method transmits without considering the transmission data sequence, it reduces the dimming level and causes a flicker phenomenon. To solve this problem, in this paper, the Dimming Improvement and Flicker Reduction Mapping technique was studied. Existing systems simply transmitted data of '0' and '1', but in this system, original data transmission channels and DIFR (Dimming Improvement and Flicker Reduction) transmission channels are assigned to RGB channels. Original data is allocated to the R channel and original data or inverse original data is allocated to the DIFR-G channel, and the DIFR-B channel maintains the maximum dimming level by transmitting through the logical operation of the R channel and the G channel. At the same time, the flicker phenomenon is prevented by preventing continuous occurrence of 'OFF' patterns. Through this, we proposed an adaptive data allocation algorithm that can faithfully play a role as a light as well as a communication function.

• Journal of Advanced Navigation Technology
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• v.24 no.2
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• pp.85-91
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• 2020

Recently, a multi-mode radar system was designed for efficient operation of unmanned aerial vehicles (UAVs) in various environments, which has the advantage of being able to integrate and utilize methods of the pulse Doppler (PD) radar and the frequency modulated continuous wave (FMCW) radar. For the range detection part of the multi-mode radar signal processor (RSP), the hardware structure using the FFT processor and the IFFT processor is required to be designed in a way that improves efficiency on the area side. In addition, given the radar application environment that requires a variety of distance resolutions, FFT processors need to support variable-length operations. In this paper, the FFT processor and IFFT processor in multi-mode RSP range estimation are designed and proposed as hardware for a single FFT processor that supports variable length operation of 16-1024 points. The proposed FFT processor designed in hardware description language (HDL) and can be implemented with 7,452 logic elements and 5,116 registers.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4B
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• pp.353-364
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• 2002

In this paper, a new onto-digital stereo object-tracking system using hierarchical digital algorithms and optical BPEJTC is proposed. This proposed system can adaptively track a moving target by controlling the convergence of stereo camera. firstly, the target is detected through the background matching of the sequential input images by using optical BPEJTC and then the target area is segmented by using the target projection mask which is composed by hierarchical digital processing of image subtraction, logical operation and morphological filtering. Secondly, the location's coordinate of the moving target object for each of the sequential input frames can be extracted through carrying out optical BPEJTC between the reference image of the target region mask and the stereo input image. Finally, the convergence and pan/tilt of stereo camera can be sequentially controlled by using these target coordinate values and the target can be kept in tracking. Also, a possibility of real-time implementation of the adaptive stereo object tracking system is suggested through optically implementing the proposed target extraction and convergence control algorithms.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.476-487
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• 2007

Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption for data storage. However, it has one main drawback of requiring an erase before updating the contents. Furthermore, flash memory can only be erased limited number of times. To overcome limitations, flash memory needs a software layer called flash translation layer (FTL). The basic function of FTL is to translate the logical address from the file system like file allocation table (FAT) to the physical address in flash memory. In this paper, a new FTL algorithm called an efficient and advanced space-management technique (EAST) is proposed. EAST improves the performance by optimizing the number of log blocks, by applying the state transition, and by using reallocation blocks. The results of experiments show that EAST outperforms FAST, which is an enhanced log block scheme, particularly when the usage of flash memory is not full.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.6
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• pp.79-86
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• 2009

In this paper, it has the performance metrics and the utility evaluation of the collusion codes about multimedia fingerprinting code based on BIBD and then the tracing algorithm of all colluders is proposed. Among the collusion codes, the bit stream of "all 0" or "all 1" are generated, also same collusion code and bit reversed code with user's fingerprinting code are generated. Thus there was occurred some problems, in which a colluder is deciding to anti-colluder or anti-colluder is deciding to colluder. In this paper, for the performance metrics and the utility evaluation of the collude codes, the experiment onto the total solution is processed by the logical collusion operation added with a partially processed averaging attack in the past papers. The proposed performance metrics and the utility evaluation about the collusion code generated from multimedia fingerprinting code based on BIBD is operated. Through the experiment, it confirmed that the ratio of colluder tracing is 100%.

• Journal of Broadcast Engineering
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• v.20 no.2
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• pp.257-264
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• 2015

In this paper, Enhanced binary block matching method for Constrained one-bit transform (C1BT) based motion estimation is proposed. Binary motion estimation exploits the Number of non-matched points (NNMP) as a block matching criterion instead of the Sum of Absolute Differences (SAD) for low complex motion estimation. The motion estimation using SAD could use the smaller block for more accurate motion estimation. In this paper the enhanced binary block matching method using smaller motion estimation block for C1BT is proposed to the more accurate binary matching. Experimental results shows that the proposed algorithm has better Peak Signal to Noise Ration (PSNR) results compared with conventional binary transform algorithms.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• Journal of KIISE
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• v.44 no.4
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• pp.399-410
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• 2017

We present a system that automatically annotates unverified Web sentences with information from credible sources. The system turns to neural theorem proving for an annotating task for cancer related Wikipedia data (1,486 propositions) with Korean National Cancer Center data (19,304 propositions). By switching the recursive module in a neural theorem prover to a word embedding module, we overcome the fundamental problem of tremendous learning time. Within the identical environment, the original neural theorem prover was estimated to spend 233.9 days of learning time. In contrast, the revised neural theorem prover took only 102.1 minutes of learning time. We demonstrated that a neural theorem prover, which encodes a proposition in a tensor, includes a classic theorem prover for exact match and enables end-to-end differentiable logic for analogous words.