• Journal of the Korea Society of Computer and Information
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• v.10 no.6 s.38
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• pp.239-252
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• 2005

Ubiquitous Sensor Network(USN) , the core technology for the Ubiquitous environments ,must be operated in the restrictive battery capacity and computing. From this cause, USN needs the lightweight design for low electric energy and the minimum computing. The previous mutual authentication. based on J$\emptyset$sang's trust model, in USN has a character that makes the lightweight mutual authentication possible in conformity with minimum computing. But, it has an imperfection at the components of representing the trust from a lightweight point of view. In this paper, we improve on the J$\emptyset$sang's trust model to apply a lightweight mutual authentication in USN. The proposed trust model in USN defines the trust information with the only degree of trust-entity(x)'s belief. The defined trust information has a superiority over the J$\emptyset$sang's trust model from a computing Point of view. because it computes information by Probability and logic operation(AND).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.459-468
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• 2003

This paper proposes a novel low-cost and high-speed Reed-Solomon (RS) decoder based on a new degree computationless modified Euclid´s (DCME) algorithm. This architecture has quite low hardware complexity compared with conventional modified Euclid´s (ME) architectures, since it can remove completely the degree computation and comparison circuits. The architecture employing a systolic away requires only the latency of 2t clock cycles to solve the key equation without initial latency. In addition, the DCME architecture using 3t＋2 basic cells has regularity and scalability since it uses only one processing element. The RS decoder has been synthesized using the 0.25${\mu}{\textrm}{m}$. Faraday CMOS standard cell library and operates at 200MHz and its data rate suppots up to 1.6Gbps. For tile (255, 239, 8) RS code, the gate counts of the DCME architecture and the whole RS decoder excluding FIFO memory are only 21,760 and 42,213, respectively. The proposed RS decoder can reduce the total fate count at least 23% and the total latency at least 10% compared with conventional ME architectures.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.1
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• pp.99-113
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• 2004

A new architecture called SAN(Storage Area Network) was developed in response to the requirements of high availability of data, scalable growth, and system performance. In order to use SAN more efficiently, most of SAN operating softwares support storage virtualization concepts that allow users to view physical storage devices attached to SAN as a large volume virtually h logical volume manager plays a key role in storage virtualization. It realizes the storage virtualization by mapping logical addresses to physical addresses. A logical volume manager also supports a snapshot that preserves a volume image at certain time and on-line reorganization to allow users to add/remove storage devices to/from SAN even while the system is running. To support the snapshot and the on-line reorganization, most logical volume managers have used table based mapping methods. However, it is very difficult to manage mapping table because the mapping table is large in proportion to a storage capacity. In this paper, we design and implement an efficient and flexible hybrid mapping method based on mathematical equations. The mapping method in this paper supports a snapshot and on-line reorganization. The proposed snapshot and on-line reorganization are performed on the reserved area which is separated from data area of a volume. Due to this strategy normal I/O operations are not affected by snapshot and reorganization. Finally, we show the superiority of our proposed mapping method through various experiments.

• Korean Journal of Cognitive Science
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• v.16 no.4
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• pp.369-386
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• 2005

Although Intelligent Tutoring System(ITS) offers individualized learning environment that overcome limited function of existent CAI, and consider many learners' variable, there is little development to be using at the sites of schools because of inefficiency of investment and absence of pedagogical content knowledge representation techniques. To solve these problem, we should study a method, which represents knowledge for ITS, and which reuses knowledge base. On the pedagogical content knowledge, the knowledge in education differs from knowledge in a general sense. In this paper, we shall primarily address the multi-complex structure of knowledge and explanation of learning vein using multi-complex structure. Multi-Complex, which is organized into nodes, clusters and uses by knowledge base. In addition, it grows a adaptive knowledge base by self-learning. Therefore, in this paper, we propose the 'Extended Neural Logic Network(X-Neuronet)', which is based on Neural Logic Network with logical inference and topological inflexibility in cognition structure, and includes pedagogical content knowledge and object-oriented conception, verify validity. X-Neuronet defines that a knowledge is directive combination with inertia and weights, and offers basic conceptions for expression, logic operator for operation and processing, node value and connection weight, propagation rule, learning algorithm.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.10-17
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• 2007

It opens a new horizon on spintronics for the potential application of MTJ as a universal logic element, to employ the magneto-logic in substitution for the transistor-based logic device. The magneto-logic based on the MTJ element shows many potential advantages, such as high density, and nonvolatility. Moreover, the MTJ element has programmability and can therefore realize the full logic functions just by changing the input signals. This magneto-logic using MTJ elements can embody the reconfigurable circuit to overcome the rigid architecture. The established magneto-logic element has been designed and fabricated on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. A 4-bit gray counter is designed to verify the magneto-logic functionality of the proposed single-layer MTJ and the simulation results are presented with the HSPICE macro-model of MTJ that we have developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2330-2336
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• 2013

Since many man-made systems consist of autonomous and interactive components, it is intrinsically difficult to analyze their abnormal behavior. The logical analysis of such a system is an indispensable process for high quality and reliable system development. In this paper, we propose an analysis method using two algebraic operations, named composition and minimization. Repetitive composition and minimization of component models with respect to a set of important events produces a new analysis model that has the same input output responses to an environment. An analysis example of the alternating bit protocol demonstrates the effectiveness of the proposed method showing that each message generated at the sender side eventually arrives to a receiver.

• Journal of The Korean Association of Information Education
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• v.18 no.1
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• pp.25-33
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• 2014

Due to the recent development of educational robot hardwares, processing speed and scalability have been greatly improved. Thus, the robot hardwares that are compatible with temperature sensor for MBL and gyro sensor made a data logging possible. Students can conduct an experiment on scientific research and prediction, collecting and data analysis with robots that can process data logging. Therefore this research constructed and adopted science project class that introduced a Smart r-Learning that utilizes Class SNS and smartphone. As a result of applying a data logging smart r-Learning to elementary school 5th graders, it has shown that the students' logical thinking ability four of the six areas have been improved in t-test.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.419-423
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• 2008

사람의 손동작은 오랫동안 하나의 언어역할을 하는 통신 수단으로 사용되어 왔다. 이러한 손동작 중에서 가장 체계를 갖춘 수화는 청각장애인이 일반인과 일상 대화를 할 수 있도록 도와주는 주요한 통신 수단이다. 하지만 건청인들의 대부분이 습득하고 있지 않아 청각장애인들과 의사소통이 거의 불가능 한 것이 현실이다. 따라서 본 논문에서는 건청인과 청각장애인들 간의 의사소통을 원활하게 하기 위해 색상 정보와 퍼지 클러스터링 알고리즘을 이용한 실시간 수화 인식 방법을 제안한다. 제안된 방법은 화상 카메라를 통해 얻어진 실시간 영상에서 YCbCr 컬러 공간에서 색차 정보에 해당하는 Cb, Cr 정보를 각각 추출한 후, 이진화한 영상과 원본 영상에서 마스크를 통한 에지를 추출한 이진화 영상에 대해 논리연산을 통해 두 손의 위치와 외곽을 추출한다. 추출된 각 정보를 조합하여 8 방향 윤곽선 추적 알고리즘을 적용하여 객체의 위치를 추적한다. 그리고 추적한 객체의 영역에 대해 형태학적 정보를 이용하여 잡음을 제거한 후, 최종적으로 두 손의 영역을 추출한다. 추출된 손의 영역은 퍼지 클러스터링 기법 중의 FCM 알고리즘을 적용하여 수화의 특징들을 분류하고 인식한다. 제안된 방법의 성능을 평가하기 위해 화상카메라를 통해 얻어진 실시간 영상을 대상으로 실험한 결과, 제안된 방법이 두 손 영역의 추출에 효과적이고 수화 인식에 있어서 가능성을 확인하였다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2003.05a
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• pp.137-140
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• 2003

캐리커처의 일반적인 의미는 어떤 사람이나 사물의 특징을 추출하여 익살스럽게 풍자한 그림이나 글이다. 다시 말해, 캐리커처는 사람의 얼굴에서 특징을 잡아 과장하거나 왜곡하여 그린 데생이라고 한다. 컴퓨터를 이용한 기존의 캐리커처 제작방법으로는, 입력 이미지 좌표의 통계적인 차이값을 이용하는 PICASSO System 방법[1], 제작자의 애매한 느낌을 퍼지 논리를 이용하여 표현하는 방법, 이미지를 와핑하는 방법, 여러 단계의 벡터 필드 변환을 이용하는 방법등이 연구되어 왔다. 본 논문에서는 실시간 또는 준비된 영상을 입력으로 받아 저장한 후, 네 단계의 과정으로 처리한 후 최종적으로 캐리커처된 이미지를 생성하게 된다. 각 단계별 처리 내용으로는 첫번째 단계에서는 영상에서 얼굴을 검출하고 두번째 단계에서는 특정 얼굴부위의 기하학적 정보를 좌표값으로 추출한다. 세번째 단계에서는 전 단계에서 얻은 좌표값으로 로컬 와핑 기법을 이용하여 영상을 변환한다. 네 번째 단계에서는 변형된 영상으로 퍼지 논리를 이용하여 보다 개선된 윤곽선 이미지로 변환하여 캐리커처 이미지를 얻는다. 본 논문에서는 영상 인식, 변환 및 윤곽선 검출 및 둥의 여러 가지 영상 처리 기법을 이용하여 기존의 캐리커처 제작 방식보다 간단하고, 복잡한 연산 과정이 없는 캐리커처 제작 시스템을 구현하였다.

• Proceedings of the KIEE Conference
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• 2003.07a
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• pp.564-566
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• 2003

전력 계통에서 안정한 전력을 공급하는 것은 매우 중요하다. 전력 계통의 오류는 전압 및 주파수를 감시함으로써 검출 가능하다. 본 논문에서는 디지털 위상 고정 루프를 이용한 전력 계통의 주파수 측정 장치를 제안하고 이를 구현한 결과를 제시하고자 한다. 제안한 주파수 측정 장치는 위상 고정 루프의 기본요소로 구성된다. 위상분별기는 배타적 논리연산을 통해 위상오차를 검출하고 위상의 앞섬 및 뒤짐의 검출이 가능하도록 설계하였으며, 전력 계통의 주파수 동특성을 고려해서 3차의 루프 필터를 설계하였다. DCO는 출력 주파수의 분해능을 고려하여 입력 신호를 정확하게 추정할 수 있도록 설계하였다. 제안한 주파수 측정 장치의 성능을 검증하기 위하여 모의실험을 통해 주파수 변동량의 측정 범위 및 정확도를 검토하였으며, FPGA와 CPU를 포함하는 하드웨어를 구현하였다. FPGA에는 Verilog HDL로 디지털 위상 고정 루프의 위상분별기와 DCO를 구현하였으며 루프필터는 소프트웨어로 구현하였다. 제안한 디지털 위상 고정 루프의 성능 검증을 위해 정밀한 함수 발생기의 출력을 인가한 후 출력 주파수를 측정한 결과 및 전력 계통에 대한 실험 결과를 제시하였다.