• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.123-131
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• 2002

In this paper, a new standard basis parallel ternary-valued multiplier circuit designed using current mode CMOS is presented. Prior to constructing the GF(3$^{ｍ}$) multiplier circuit, we provide a GF(3) adder and a GF(3) multiplier with truth tables and symbolize them, and also design them using current mode CMOS circuit. Using the basic ternary operation concept, a ternary adder and a multiplier, we develop the equations to multiply arbitrary two elements over GF(3$^{ｍ}$). Following these equations, we can design a multiplier generalized to GF(3$^{ｍ}$). For the proposed circuit in this paper, we show the example in GF(3$^{3}$). In this paper, we assemble the operation blocks into a complete GF(3$^{ｍ}$) multiplier. Therefore the proposed circuit is easy to generalize for m and advantageous for VLSI. Also, it need no memory element and the latency not less fewer than other circuit. We verify the proposed circuit by functional simulation and show its result.

• Journal of Educational Research in Mathematics
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• v.22 no.4
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• pp.477-494
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• 2012

This study is to review the content organization and developmental ways of the unit on the mixed calculations and explore the alternatives on the basis of students' responsive examples and error patterns with relation to the mixed calculations, mnemonics of PEMDAS and historical context with relation to the order of operations. Then I analyzed the textbook and manual for teachers of the unit of mixed calculations of fourth grade and improvement about teaching the mixed calculations. First, I pointed out illogical connection between practical problem and rules of order of operations. Second, I suggested constructing a textbook by considering conventional character of order of operations. Third, I pointed out the importance of structural understanding of an expression of mixed calculations and various strategies with relation to teaching and learning. This study is suggestive for textbook development of the mixed calculations.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.6
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• pp.813-818
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• 2021

This paper proposes an optimized hardware implementation method for existing CIE1931 color gamut control algorithm. Among the post-processing methods of dehazing algorithms, existing algorithm with relatively low computations have the disadvantage of consuming many hardware resources by calculating large bits using Split multiplier in the computation process. The proposed algorithm achieves computational reduction and hardware miniaturization by reducing the predefined two matrix multiplication operations of the existing algorithm to one. And by optimizing the Split multiplier computation, it is implemented more efficient hardware to mount. The hardware was designed in the Verilog HDL language, and the results of logical synthesis using the Xilinx Vivado program were compared to verify real-time processing performance in 4K environments. Furthermore, this paper verifies the performance of the proposed hardware with mounting results on two FPGAs.

• Proceedings of the Korean Society for Agricultural Machinery Conference
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• 2017.04a
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• pp.161-161
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• 2017

스마트 시설환경의 제어 요소는 난방기, 창 개폐, 수분/양액 밸브 개폐, 환풍기, 제습기 등 직접적으로 시설환경의 조절에 관여하는 인자와 정보 교환을 위한 통신, 사용자 인터페이스 등 간접적으로 제어에 관련된 요소들이 복합적으로 존재한다. PID 제어와 같이 하는 수학적 논리를 바탕으로 한 제어와 전문 관리자의 지식을 기반으로 한 비선형 학습 모델에 의한 제어 등이 공존할 수 있다. 이러한 다양한 요소들을 복합적으로 연동시키기 위해선 기존의 시퀀스 기반 제어 방식에는 한계가 있을 수 있다. 관행의 방식과 같이 시계열 상에서 획득한 충분한 데이터를 이용하여 제어의 양과 시점을 결정하는 방식은 예외 상황에 충분히 대처하기 어려운 단점이 있을 수 있다. 이러한 예외 상황은 자연적인 조건의 변화에 따라 불가피하게 발생하는 경우와 시스템의 오류에 기인하는 경우로 나뉠 수 있다. 본 연구에서는 실시간으로 변하는 시설환경 내의 다양한 환경요소를 실시간으로 분석하고 상응하는 제어를 수행하여 수학적이며 예측 가능한 논리에 의해 준비된 제어시스템을 보완할 방법을 연구하였다. 과거의 고성능 컴퓨팅(HPC; High Performance Computing)은 다수의 컴퓨터를 고속 네트워크로 연동하여 집적적으로 연산능력을 향상시킨 기술로 비용과 규모의 측면에서 많은 투자를 필요로 하는 첨단 고급 기술이었다. 핸드폰과 모바일 장비의 발달로 인해 소형 마이크로프로세서가 발달하여 근래 2 Ghz의 클럭 속도에 이르는 어플리케이션 프로세서(AP: Application Processor)가 등장하기도 하였다. 상대적으로 낮은 성능에도 불구하고 저전력 소모와 플랫폼의 소형화를 장점으로 한 AP를 시설환경의 실시간 제어에 응용하기 위한 방안을 연구하였다. CPU의 클럭, 메모리의 양, 코어의 수량을 다음과 같이 달리한 3가지 시스템을 비교하여 AP를 이용한 마이크로 클러스터링 기술의 성능을 비교하였다.1) 1.5 Ghz, 8 Processors, 32 Cores, 1GByte/Processor, 32Bit Linux(ARMv71). 2) 2.0 Ghz, 4 Processors, 32 Cores, 2GByte/Processor, 32Bit Linux(ARMv71). 3) 1.5 Ghz, 8 Processors, 32 Cores, 2GByte/Processor, 64Bit Linux(Arch64). 병렬 컴퓨팅을 위한 개발 라이브러리로 MPICH(www.mpich.org)와 Open-MP(www.openmp.org)를 이용하였다. 2,500,000,000에 이르는 정수 중 소수를 구하는 연산에 소요된 시간은 1)17초, 2)13초, 3)3초 이었으며, $12800{\times}12800$ 크기의 행렬에 대한 2차원 FFT 연산 소요시간은 각각 1)10초, 2)8초, 3)2초 이었다. 3번 경우는 클럭속도가 3Gh에 이르는 상용 데스크탑의 연산 속도보다 빠르다고 평가할 수 있다. 라이브러리의 따른 결과는 근사적으로 동일하였다. 선행 연구에서 획득한 3차원 계측 데이터를 1초 단위로 3차원 선형 보간법을 수행한 경우 코어의 수를 4개 이하로 한 경우 근소한 차이로 동일한 결과를 보였으나, 코어의 수를 8개 이상으로 한 경우 앞선 결과와 유사한 경향을 보였다. 현장 보급 가능성, 구축비용 및 전력 소모 등을 종합적으로 고려한 AP 활용 마이크로 클러스터링 기술을 지속적으로 연구할 것이다.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.89-94
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• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• School Mathematics
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• v.9 no.1
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• pp.99-117
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• 2007

In this paper it is discussed how children develop their logical reasoning beyond difficulties in the process of making sense of division with decimals in the classroom setting. When we consider the gap between mathematics at elementary and secondary levels, and given the logical nature of mathematics at the latter levels, it can be seen as important that the aspects of children's logical development in the upper grades in elementary school should be clarified. This study focuses on the teaching and learning of division with decimals in a 5th grade classroom, because it is well known to be difficult for children to understand the meaning of division with decimals. It is suggested that children begin to conceive division as the relationship between the equivalent expressions at the hypothetical-deductive level detached from the concrete one, and that children's explanation based on a reversibility of reciprocity are effective in overcoming the difficulties related to division with decimals. It enables children to conceive multiplication and division as a system of operations.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.107-115
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• 2014

The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.

• Transactions of the Korean Society of Mechanical Engineers
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• v.16 no.7
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• pp.1234-1243
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• 1992

A systematic procedure to design fuzzy PID controllers is developed in this paper. The concept of local fuzzy control cell is proposed by introducing both an adequate global control rule and membership functions to simplify a fuzzy logic controller. Fuzzy decision is made by using algebraic product and parallel firing arithematic mean, and a defuzzification strategy is adopted for improving the computational efficiency based on nonfuzzy micro-processor. A direct method, transforming the typical output of quasi-linear fuzzy operator to the digital compensator of PID form, is also proposed. Finally, the proposed algorithm is applied to an DC-servo motor. It is found that this algorithm is systematic and robust through computer simulations and implementation of controller using Intel 8097 micro-processor.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.30-39
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• 2002

In this paper, we proposed a new circuit construction method that reduces the number of circuit devices of fuzzy controller. Sasaki had defined a new operator to eliminate the divide circuit comparing with the center of gravity method which often using to design the fuzzy controller. In this paper we obtained the more compacted fuzzy controller's circuit by using the proposed definition of fuzzification and defuzzification than using the Sasaki's method and the fuzzification and defuzzification are reverse operation each other. Using these definitions we exhibit the new design method and circuit structure that can eliminate the bounded product(BP) circuit included in Sasaki's circuit. Using the proposed method to level controlling of the water tank, we verified the fuzzy controller's performance by using existent method and proposed method. As a result that are calculated by using the Proposed fuzzy controller to level controlling of the water tank, total numbers of blocks and devices were decreased. If the number of variables and antecedents are Be11ing larger, this method is more efficient.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.640-654
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• 1996

This paper presents a synthesis method for multi-level Reed-Muller circuits using BDDs(Binary Decision Diagrams). The existing synthesis tool for Reed circuits, FACTOR, is not appropriate to the synthesis of large circuits because it uses matrix (map-type) to represent given logic functions, resulting in the exponential time and space in number of imput to the circuits. For solving this problems, a syntheisis method based on BDD is presented. Using BDDs, logic functions are represented compactly. Therefor storage spaces and computing time for synthesizing logic functions were greatly decreased, and this technique can be easily applied to large circuits. Using BDD representations, the proposed method extract best patterns to minimize multi-level Reed Muller circuits with good performance in area optimization and testability. Experimental results using the proposed method show better performance than those using previous methods〔2〕. For large circuits of considering the best input partition, synthesis results have been improved.