• Journal of IKEEE
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• v.20 no.2
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• pp.184-187
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• 2016

In this paper, we propose the sensor and the signal duplicator for the automatic building control. Developed duplicator realizes the sensor data collection apparatus and mimics the measured data and, thus, reduces the construction cost by using logical communication layer. Furthermore, the system supports the open protocols and can be associated with HMI(Human Machine Interface) used on the market. Developed duplicator is proved to be functional within the real environment. Measurement error rate, operating temperature, and operating humidity show very good results by the certified testing apparatus and organization.

• Journal of the Korea Society for Simulation
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• v.21 no.4
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• pp.35-46
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• 2012

As complexity of real-time systems is being increased ad hoc approaches to analysis of such systems would have limitations in completeness and coverability for states space search. Formal means using a model-based approach would solve such limitations. This paper proposes a model-based formal method for logical analysis, such as safety and liveness, of real-time systems at a discrete event system level. A discrete event model for real-time systems to be analyzed is specified by DEVS(Discrete Event Systems Specification) formalism, which specifies a discrete event system in hierarchical, modular manner. Analysis of such DEVS models is performed by Communicating DEVS (C-DEVS) formalism of a timed global state transition specification and an associated analysis algorithm. The C-DEVS formalism and an associated analysis algorithm guarantees that all possible states for a given system are visited in an analysis phase. A case study of a safety analysis for a rail road crossing system illustrates the effectiveness of the proposed method of the model-based approach.

• Journal of the Korea Society for Simulation
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• v.23 no.2
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• pp.73-84
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• 2014

Recently, researches on the application of IT technology to various fields including traditional industries are becoming more popular. One challenge in the field of education is to understand the way how technology may support learning, and research on self-directed learning has been accelerated by integrating education and IT technology. The process of self-directed learning in e-learning applications such as Car Maintenance Training is very difficult and complicated. Previous studies on car maintenance training applications provided simple training scenarios with predetermined action sequences. To incorporate self-directed learning in car maintenance training, however, trainees must be able to perform various maintenance operations himself and experience various situations. To provide such functionality, it is necessary to obtain an accurate response for various operations of trainees, but it requires complicated calculations with respect to varieties in the electrical and mechanical processes of a car. In this paper, we develop a logic simulation agent using JESS inference engine in which self-directed learning is achieved by capturing the behavior of trainees and simulating car operations without complicated physical simulations in car maintenance training.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1301-1308
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• 2012

In this paper, the low-power clock generator synchronized with the AC power signal using the adiabatic dynamic CMOS logic (ADCL) buffer is proposed for adiabatic logics. To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the ADCL, the clock signal of logic circuits should be synchronized with the AC power source. The clock signal for an adiabatic charging and discharging with the AC power signal was generated with the designed Schmitt trigger circuit and ADCL frequency divider using the ADCL buffer. From the simulation result, the power consumption of the proposed clock generator was estimated with approximately 1.181uW and 37.42uW at output 3kHz and 10MHz respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Proceedings of the Korean Institute of Industrial Safety Conference
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• 2003.05a
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• pp.173-178
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• 2003

화재감지시스템은 화재로부터 발생하는 열과 연기 등을 감지하여 화재발생을 조기에 관계자에게 경보하여 주는 시스템이다. 현재 이러한 화재감지시스템은 일정 규모 이상의 건축물에 필수적으로 설치되어 있으며 이 시스템으로 많은 인명과 재산이 보호되고 있다. 그러나 현재 설비되고 있는 화재감지시스템은 화재 시에 발생되는 열, 연기 등에 대하여 감지기회로에서의 미리 지정한 고정값과의 비교를 통하여 정해진 기준을 넘을 경우 화재로 판정한다. 그러나 고정값을 기준으로 신호를 발신하게 되어있는 화재감지기의 동작은 상황에 따라 불확실한 경우가 발생한다.(중략)

• 전기의세계
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• v.37 no.1
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• pp.55-62
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• 1988

본 연구에서는 현재 IBM PC등에 사용되는 8088프로세서의 16비트버젼인 8086프로세서의 ICE를 설계 제작하였다. 8088프로세서와 8086프로세서는 그 내부 기능이 동일하기 때문에 어셈블러나 링커등의 소프트웨어 개발장비들을 IBM PC에서 지원받을 수 있으므로 IBM PC에 연결된 ICE는 전체적으로 하나의 MDS시스템을 구성할 수 있다. 제작된 ICE는 1) 테스트하려는 시스템의 메모리에 대한 읽기 및 쓰기, 2) 테스트프로그램의 실제 조건에서의 수행, 3) 디버깅 기능, 4) ICE의 메모리 영역을 테스트하려는 시스템에서 활용하도록하는 기능 등을 수행할 수 있도록 하였다. 또 8086프로세서는 싱글프로세서모드와 멀티프로세서모드의 두가지 동작 모드가 있는데 싱글프로세서모드에서 동작될 수 있도록 설계되었으며 ICE의 기능 수행을 위한 논리 회로의 구성과 이해에 주안점을 두었다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.1-7
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• 2007

An MTJ element not only computes Boolean function but also stores the output result in itself. We can make the most use of magneto-logic's merits by employing the magneto-logic in substitution for the sequential logic as well as the combinational logic. This unique feature opens a new horizon for potential application of MTJ as a universal logic element. Magneto-logic circuits using MTJ elements are more integrative and non-volatile. This paper presents novel 3-bit magneto-logic up/down counters and presents simulation results based on the HSPICE macro-model of MTJ that we have developed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.20-27
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• 1999

In many synthesis applications, the structure of the synthesized circuit is derived from its BDD functional representation. When synthesizing incompletely specified functions, it is useful to minimize the size of these BDDs using don't cares. In this paper, we present two BDD minimization heuristics that target these synthesis applications. Experimental results show that new techniques yield significantly smaller BDDs compared to existing techniques with manageable run-times.