DOI QR코드

DOI QR Code

Logical Analysis of Real-time Discrete Event Control Systems Using Communicating DEVS Formalism

C-DEVS형식론을 이용한 실시간 이산사건 제어시스템의 논리 해석 기법

  • Received : 2012.08.23
  • Accepted : 2012.11.12
  • Published : 2012.12.31

Abstract

As complexity of real-time systems is being increased ad hoc approaches to analysis of such systems would have limitations in completeness and coverability for states space search. Formal means using a model-based approach would solve such limitations. This paper proposes a model-based formal method for logical analysis, such as safety and liveness, of real-time systems at a discrete event system level. A discrete event model for real-time systems to be analyzed is specified by DEVS(Discrete Event Systems Specification) formalism, which specifies a discrete event system in hierarchical, modular manner. Analysis of such DEVS models is performed by Communicating DEVS (C-DEVS) formalism of a timed global state transition specification and an associated analysis algorithm. The C-DEVS formalism and an associated analysis algorithm guarantees that all possible states for a given system are visited in an analysis phase. A case study of a safety analysis for a rail road crossing system illustrates the effectiveness of the proposed method of the model-based approach.

실시간 시스템의 복잡도가 증가함에 따라 임시방편적 시스템 해석 방법은 시스템 동작 영역 전체를 완전하게 분석하는 데는 한계가 있다. 모델링을 기반으로 한 정형 기법은 그러한 한계점을 극복 할 수 있다. 본 논문은 모델 기반 정형 기법을 이용하여 실시간 시스템의 안전성 및 필연성 등과 같은 논리적 타당성을 이산 사건 모델 수준에서 분석하는 방법을 제안한다. 먼저, 분석 대상 실시간 시스템은 이산사건 수준에서 계층적으로 모듈화하여 모델을 명세하는 수학적 형식론인 DEVS (Discrete Event Systems Specification) 형식론으로 기술된다. 다음으로, 기술된 DEVS 모델은 시간 명세가 포함된 전역 상태 공간을 표현하는 C-DEVS (Communicating DEVS) 형식론으로 표현한 후 C-DEVS 형식론의 해석 알고리즘을 통해 시스템 동작을 분석된다. 제안된 C-DEVS 형식론 및 해석 알고리즘은 주어진 시스템의 동작 특성을 분석하는 과정에서 시스템의 상태 공간을 완전하게 빠짐없이 탐색하는 것을 보장한다. 간단한 건널목 제어 시스템의 안전성 분석 사례 연구를 통하여 제안된 모델 기반 해석 기법의 효율성을 예시 하였다.

Keywords

References

  1. Leveson NG, Stolzy JL. Safety Analysis Using Petri Nets. IEEE Trans. Software Engineering 1987; SE-13: 386-397. https://doi.org/10.1109/TSE.1987.233170
  2. Song HS, Kim TG. Application of Real-Time DEVS to Analysis of Safety-Critical Embedded Control Systems: Railroad Crossing Control Example. Simulation 2005; 81: 119-136. https://doi.org/10.1177/0037549705052229
  3. Bengtsson J, Yi W. Timed Automata: Semantics, Algorithms and Tools. LNCS 2004; 3098: 87-124.
  4. Boucheneb H, Barkaoui K. Relevant Timed Schedules/Clock Vectors for Constructing Time Petri Net Reachability Graphs. Discrete Event Dynamic Systems 2011; 21: 171-204. https://doi.org/10.1007/s10626-011-0100-4
  5. Zeigler BP, Kim TG, Praehofer H. Theory of Modeling and Simulation, Orlando, FL: Academic 2000.
  6. Lee WB, Kim TG. Ordering Method for Reducing State Space in Compositional Verification. in 1999 IEEE International Conference on Systems, Man, and Cybernetics (IEEE SMC '99), Tokyo, Japan 1999; I-806-I-811.
  7. Song HS, Kim TG. Safety Analysis of Computer-controlled Real-time Systems with Message Loss Using Communicating DEVS Models. AsiaSim 2012, Part I, Communications in Computer and Information Science, Springer-Verlag Berlin Heidelberg 2012; 323: 480-489.
  8. Sung CH, Koo J, Kim TG, Kim KH. Verification of Automatic PAR Control System using DEVS formalism, Journal of Korea Simulation Society 2012; 21: 1-9. https://doi.org/10.9709/JKSS.2012.21.3.001
  9. Saadawi H, Wainer G. Verification of Real-Time DEVS Models, Proceedings of the 2009 Spring Simulation Multiconference, Society for Computer Simulation International 2009; Article no. 143.
  10. Choi CB, Kim TG. Software Formal Verification Methodology using Aspect DEVS Verification Framework, Journal of Korea Simulation Society 2009; 18: 113-122.