• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.46-53
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• 2011

This paper presents an equalizer reducing CCI(cell-to-cell interference) in MLC NAND flash memory. The CCI is a critical factor which affects occurring data errors in a cell, when surrounding cells are programed. We derived a characteristic equation for CCI considering write procedure of data that is similar with signal equalizing. The model considers the floating gate capacitance coupling effect, the direct field effect, and programming methods of the MLC NAND flash memory. We verify the proposed equalizer comparing with the measured data of 1-block MLC NAND flash memory. As the simulation result, the equalizer shows an error correction ratio about 60% under 20nm NAND process.

• Proceedings of the Korean Information Science Society Conference
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• 2007.06c
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• pp.69-74
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• 2007

플래시 메모리는 하드디스크와 다른 물리적 특성을 가지고 있다. 대표적으로 덮어쓰기가 되지 않고 데이터를 읽고 쓰는 단위와 지우는 단위가 서로 다르다. 이러한 물리적 제약을 소프트웨어적으로 보완해주기 위해서 플래시 메모리를 사용하는 시스템에서는 대부분 Flash Translation Layer (FTL)을 사용한다. 지금까지 FTL 알고리즘의 대부분이 임의 쓰기 패턴보다 순차 쓰기 패턴에 훨씬 더 효율적으로 작용한다. 그러나 B-트리와 같은 자료구조에서는 일반적으로 순차 쓰기 패턴 보다는 임의 쓰기 패턴이 발생된다. 따라서 플래시 메모리상에서 B-트리를 관리할 경우 FTL에 비효율적인 쓰기 패턴을 생성하게 된다. 본 논문에서는 플래시 메모리상에서 B-트리와 같은 자료구조를 효율적으로 저장 관리하기 위한 새로운 방식을 제안한다. 새로운 방식은 B-트리에서 발생되는 임의 쓰기를 플래시 메모리상의 버퍼를 이용하여 FTL에 효율적인 순차 쓰기를 발생시킨다. 실험 결과, 본 논문에서 제안하는 방식은 기존의 방식보다 플래시 메모리에서 발생되는 쓰기 및 블록소거 연산 횟수를 60%이상 감소시킨다.

• Proceedings of the Korean Information Science Society Conference
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• 2012.06c
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• pp.72-74
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• 2012

최근 스마트폰, 태블릿이 보편화되고 플래시 메모리가 모바일기기의 저장장치로 많이 사용되면서 저장되는 데이터에 대한 보안성도 높아지고 있다. 모바일 기기를 사용하는 사용자 입장에서 더 이상 필요치 않은 목적으로 데이터를 삭제하고 유출을 막기 위해 파일 와이핑 기법을 사용한다. 하지만 일반적인 와이핑 기법은 하드디스크 특성을 바탕으로 수행되기 때문에 플래시 메모리를 사용할 경우 플래시 메모리 특성으로 인해 와이핑 이후 기존정보가 존재하기 때문에 복구가 가능하다. 최근 플래시 메모리 데이터의 보안성을 요구하는 기법이 연구된바 있지만 불필요한 오버헤드 및 기법 적용이 제한적이라는 문제가 있다. 본 논문에서는 다양한 FTL에 적용이 가능한 플래시 메모리상의 저장된 데이터에 대한 와이핑 수행이후 복구 방지 기법을 제안한다. 이 기법은 임의 값을 이용한 블록 치환 알고리즘을 통해 테이블을 생성하고 테이블을 이용해서 플래시 메모리를 블록 단위로 치환을 하여 수행한다.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.4
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• pp.215-225
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• 2010

The NAND flash memory based SSDs are considered to replace the existing HDDs. To maximize the I/O performance, SSD is composed of several NAND flash memories in parallel. However, to adopt the hybrid mapping scheme in SSD may cause degradation of the I/O performance. In this paper, we propose a new mapping scheme for the SSD called WADPM. WADPM loads only necessary mapping information into RAM and dynamically adjusts the size of mapping information in the RAM. So, WADPM avoids the shortcoming of page-level mapping scheme that requires too large mapping table. Performance evaluation using simulations shows that I/O performance of WADPM is 3.5 times better than the hybrid-mapping scheme and maximum size of mapping table of WADPM is about 50% in comparison with the page-level mapping scheme.

• 정보화사회
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• s.180
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• pp.20-21
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• 2006

현재 모바일기기용 스토리지 사장은 낸드 플래시와 소형 HDD가 경쟁하고 있다. 음악플레이어를 중심으로 이 두 스토리지의 경쟁이 어제오늘 시작된 것은 아니지만 최근 낸드 메모리의 영역이었던 휴대폰에 소형HDD가 진출했다는 건 주목할 만한 일이다. 음악 플레이어 지원 휴대폰이 인기를 누리면서 벌어지는 추세이다.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.78-87
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• 2013

NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

• Journal of KIISE
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• v.43 no.2
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• pp.177-185
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• 2016

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.10
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• pp.245-250
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• 2019

The use of NAND flash memory has increased rapidly due to the development of mobile fields. However, NAND flash memory has a limited lifespan, so studies are underway to predict its lifespan. Workload is one of the factors that significantly affect the life of NAND flash memory, and workload analysis studies in mobile environments are insufficient. In this paper, we analyze the distribution of workload in the mobile environment by collecting traces generated by using Android-based smartphones. The collected traces can be divided into three groups of hotness. Also they are distributed in the form of heavy tails. We fit this to the Pareto, Lognormal, and Weibull distributions, and Traces are closest to the Pareto distribution.

• Journal of KIISE:Computing Practices and Letters
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• v.14 no.3
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• pp.256-260
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• 2008

This paper describes an improvement of mount-time delay in NAND Flash file systems. To improve file system mount performance, this work configures a hierarchical storage system with byte-addressable NVRAM and NAND Flash memory, and let the meta data of a file system allocated in the NVRAM. Since the meta data are stored in NVRAM supporting data integrity some of the items, which are stored in Spare area and Object Header area of NAND Flash memory to control meta data of NAND Flash file system, could be eliminated. And also, this work eliminates the scanning operation of the Object Header area of previous work FRASH1.0. The scanning operation is definitely required to find out the empty Object Header address for storing the Object Header data and provokes a certain amount of performance loss in file generation and deletion. In this work, an implemented file system, so-called FRASH1.5, is demonstrated, featuring new data structures and new algorithms. The mount time of FRASH1.5 becomes twice as fast as that of the FRASH1.0. The performance in file generation gets improved by about $3{\sim}8%$. In particular, for most large-size files, the FRASH1.5 has 8 times faster mount time than YAFFS, without any performance loss as seen in the file generation.

• Journal of the Korea Society of Computer and Information
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• v.20 no.5
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• pp.1-12
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• 2015

NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.