• Journal of Advanced Marine Engineering and Technology
• /
• v.39 no.4
• /
• pp.363-367
• /
• 2015

In this study, a high performance Bubble Jet Loop Heat Pipe (BJLHP) was developed using the enhanced nucleate boiling surfaces in an evaporating section. A sintered tube and GEWA-T(Wieland) tube were used enhance nucleate boiling. The thermal performance of these BJLHP was compared with the conventional smooth tube BJLHP with an effective thermal conductivity. This experiment was conducted under the following conditions : working fluid, charging ratio and input power of R-141b, 50%vol., 75W and 100W, respectively. As a result, the effective thermal conductivity of BJLHP with a sintered tube in the evaporating section was 300% higher than the smooth tube BJLHP.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.12
• /
• pp.91-102
• /
• 2005

Recently, concurrent error detection for the processor becomes important. But it imposes too much overhead to adopt concurrent error detection capability on the system. In this paper, a new approach to resolve the problems of concurrent error detection is proposed. A loop detection scheme is introduced to reduce the repetitive loop iteration and memory access. To reduce the memory overheat an offset to calculate the target address of branching node is proposed. Performance evaluation shows that the new architecture has lower memory overhead and frequency of memory access than previous works. In addition, the new architecture provides the same error coverage and requires nearly constant memory size regardless of the size of the application program. Consequently, the proposed architecture can be used as an cost effective method to detect control flow errors in the commercial on the shelf products.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.3
• /
• pp.585-593
• /
• 2017

In this paper, we propose a deblocking filter hardware architecture for low-power HEVC (High-Efficiency Video Coding) in-loop for mobile systems. HEVC performs image compression on a block-by-block basis, resulting in blockage of the image due to quantization error. The deblocking filter is used to remove the blocking phenomenon in the image. Currently, UHD video service is supported in various mobile systems, but power consumption is high. The proposed low-power deblocking filter hardware structure minimizes the power consumption by blocking the clock to the internal module when the filter is not applied. It also has four parallel filter structures for high throughput at low operating frequencies and each filter is implemented in a four-stage pipeline. The proposed deblocking filter hardware structure is designed with Verilog HDL and synthesized using TSMC 65nm CMOS standard cell library, resulting in about 52.13K gates. In addition, real-time processing of 8K@84fps video is possible at 110MHz operating frequency, and operation power is 6.7mW.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.17 no.1
• /
• pp.116-123
• /
• 2003

In this paper, interleaved boost converter is applied as a pre-regulator in switched mode power supply. The pre-regulator plays a role to improve power factor. Interleaved Boost Power Factor Corrector(IBPFC) can reduce input current ripple as a single voltage control loop only without inner current loop, because input current is divided each 50% by two switching devices. Each converter cell is also operated in discontinuous current mode and inductor current of each converter is discontinuous. Total input current which is composed by each converter cell is continuous current. Thus, IBPFC is able to improve input current ripple. IBPFC operating in discontinuous current mode can be classified as six modes from switching state and be carried out state space averaging small signal modeling. A control transfer function is obtained according to the modeling. Single voltage control loop is also constructed by the control transfer function. From experimental result, improvement of power factor and input current ripple are verified.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.543-545
• /
• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.44 no.1
• /
• pp.74-84
• /
• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.24 no.2
• /
• pp.1-6
• /
• 2024

In this paper, we designed and implemented the security network NVR system that can flexibly use the internal network and VPN network. In general, the NVR systems that only use internal networks cannot be access from the outside, which has the disadvantage of unnecessary inspections and inability to access from the outside. External access has made possible using the VPN security network, and a NVR system software was designed and implemented so that the existing internal network could be used. We compared with the NVR system usage environment in the internal network through the client and the NVR system. It also has implemented usage environment with the VPN network through the mobile APP, and confirmed that the same NVR was operating normally with the same functions. We also studied on IP based NVR for flexible access with closed loop network based on VPN system.

• Transactions of the Korean Society for Noise and Vibration Engineering
• /
• v.24 no.3
• /
• pp.171-179
• /
• 2014

Sunroof buffeting is one of the most critical issues in the vehicle wind noise phenomena. The experimental approach to solve this issue typically requires a lot of time and resources. To reduce time and cost, the numerical approach could be taken, which can also privide more insights into physical phenomena involved in sunroof buffeting, only if the accuracy in its predictions are guranteed. The benchmark test of various numerical solvers is carried out for the buffeting behavior of a simplified vehicle body, the Hyundai simplified model(HSM). The results of each solver are compared to the experimental measurements in a Hyundai aeroacoustic wind tunnel(HAWT) at various wind speeds. In particular, acoustic response tests were performed and the results were provided prior to all simulations in order to consider the real world effects that could introduce discrepancies between the numerical and experimental approaches. Through this study, most solvers can demonstrate an acceptable accuracy level for actual commercial development and high precision experimental data and computational prediction priories can be shared in order to promote the numerical accuracy level of each numerical solver.

• Geophysics and Geophysical Exploration
• /
• v.6 no.3
• /
• pp.143-152
• /
• 2003

Among the various geophysical approaches to identify the leakage of leachate with conductivity variation, conventional electrical resistivity survey has been mainly used at waste landfill. We adopted small-loop electromagnetic (EM) survey using multi-frequencies in parallel with electrical resistivity survey to delineate the leakage of leachate through the shallow soil layer at a waste landfill in Jeju Island, and also with self-potential monitoring to detect the streaming potential produced by the movement of leachate. There were no evidences of leakage from waste landfill according to the results of the electrical resistivity survey and SP monitoring, and it was also true from the results of water quality analysis at stream around waste landfill periodically. On the other hand, the results of one-dimensional inversion of spatially-filtered small-loop EM survey data showed the anomalous zone of low resistivity with depth both around and inner waste landfill.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.41 no.1
• /
• pp.9-16
• /
• 2004

In this paper, we propose a robust controller for robot manipulators with parametric uncertainties using feature-based visual servo control system. In order to improve trajectory error of the robot manipulators due to the parameter variation, integral action is included in the dynamic control of part in inner subroutine of the control system. This integral action also reduces feature error in the steady state. The stability analysis of the closed-loop system is shown by the Lyapunov method. The effectiveness of the proposed method is shown by simulation and experimental results on the 5 link robot manipulator with two degree of freedom.