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A Cost-effective Control Flow Checking using Loop Detection and Prediction  

Kim Gunbae (Yonsei University, Department of Electrical and Electronic Engineering)
Ahn Jin-Ho (Yonsei University, Department of Electrical and Electronic Engineering)
Kang Sungho (Yonsei University, Department of Electrical and Electronic Engineering)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.12, 2005 , pp. 91-102 More about this Journal
Abstract
Recently, concurrent error detection for the processor becomes important. But it imposes too much overhead to adopt concurrent error detection capability on the system. In this paper, a new approach to resolve the problems of concurrent error detection is proposed. A loop detection scheme is introduced to reduce the repetitive loop iteration and memory access. To reduce the memory overheat an offset to calculate the target address of branching node is proposed. Performance evaluation shows that the new architecture has lower memory overhead and frequency of memory access than previous works. In addition, the new architecture provides the same error coverage and requires nearly constant memory size regardless of the size of the application program. Consequently, the proposed architecture can be used as an cost effective method to detect control flow errors in the commercial on the shelf products.
Keywords
On-line test; Watchdog processor; Transient fault; Loop detection; Control flow error;
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