• Journal of Drive and Control
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• v.15 no.4
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• pp.55-60
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• 2018

Force-controlled electro-hydrostatic actuators have to exhibit high backdrivability, to quickly compensate for force control errors caused by externally disturbed rod movement. To obtain high backdrivability, the servomotor for driving the hydraulic pump, should rotate exactly to such a revolution to compensate for force control errors, compressing or decompressing cylinder chambers. In this study, we proposed a modified velocity control structure, including a robust internal-loop compensator (RIC)-based velocity controller, for the servomotor to improve backdrivability of a force-controlled EHA. Performance improvement was confirmed experimentally, wherein sinusoidal velocity disturbance was applied to the force-controlled EHA, with constant reference input. Its dynamic force control errors reduced effectively, with the proposed control scheme, compared to test results with a conventional motordriver, for motor velocity control.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.1
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• pp.1-6
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• 2019

An extremely small size multi-loop phase-locked loop(PLL) keeping phase noise performances has been proposed. It has been designed to have the loop filter made of small single capacitor with multiple Frequency Voltage Converters (FVCs) because the main goal is to make the size of the proposed PLL extremely small. Multiple FVCs which are connected to voltage controlled oscillator(VCO) make multiple negative feedback loops in PLL. Those multiple negative feedback loops enable the PLL with the loop filter made of an extremely small size single capacitor operate stably. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the 1.6ps jitter and $10{\mu}s$ locking time.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.15 no.2
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• pp.89-94
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• 2022

In this paper, a discrete-time loop filter(DLF) phase-locked loop with a Frequency Fluctuation Converting Circuit(FFCC) has been proposed. Discrete-time loop filter can improve spur characteristic by connecting the charge pump and voltage oscillator discretely unlike a conventional continuous-time loop filter. The proposed PLL is designed to operate stably by the internal negative feedback loop including the SSC acting as a negative feedback to the discrete-time loop filter of the external negative feedback loop. In addition, the phase noise is further improved by reducing the magnitude of the loop filter output voltage variation through the FFCC. Therefore, the magnitude of jitter has been reduced by 1/3 compared to the conventional structure. The proposed phase locked loop has been simulated with Hspice using the 1.8V 180nm CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.71-72
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• 2015

본 논문에서는 CPW(Coplanar waveguide) 급전되는 평면 루프 슬롯을 2.45 GHz 대역 Wi-Fi용으로 소형화 설계하는 방법에 대해 연구하였다. 제안된 구조는 직사각형 형태의 CPW 급전 루프 슬롯 안테나를 기본형으로 하여 내부 패치에 슬롯을 좌우 대칭으로 여러 개 수직 방향으로 배치한 안테나이며, FR4 기판의 한 면에 인쇄된다. 여러 가지 파라미터 값들이 안테나의 특성에 미치는 영향을 관찰하고 기존 루프 슬롯 안테나를 소형화하는 방법에 대해 연구하였다. FR4 기판에 $80mm{\times}50mm$ 크기로 2.45 GHz 대역용으로 설계된 안테나의 특성을 시뮬레이션을 통해 분석하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.2
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• pp.116-127
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• 2003

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an Internal model controller The Internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.1-11
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• 2007

In this paper, a new fully digital control method for UPS inverter, which is based on the double control loop such as the outer voltage control loop and inner current control loop, is proposed. In the proposed control system, overshoots and oscillations due to the computation time-delay are compensated by explicit incorporation of the time-delay in the current control loop transfer function. The inner current control loop is adopted by an internal model controller. The internal model controller is designed to a second order deadbeat reference-to-output response which means that its response reaches the reference in two sampling time including computational time-delays. The outer voltage control loop employing P-Resonance controller is proposed. The resonance controller has an infinite gain at resonant frequency, and the resonant frequency is set to the fundamental frequency of the reference voltage in this paper. Thus the outer voltage control loop causes no steady state error as regard to both magnitude and phase. The effectiveness of the proposed control system has been verified by the simulation and experimental results respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.10
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• pp.934-940
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• 2011

A novel reconfigurable beam steering antenna using double loops is proposed. The double loop antenna has a superposed beam which is produced by combining the in-phase beam in the inner loop with the out-of-phase beam in the outer loop. Also, the doble loop antenna uses two artificial switches to connect between inner loop and outer loop, and has the beam directions of three separate cases(Case 1, Case 2, Case 3) by changing ON/OFF states of switches. The operation frequency of the antenna is 14.5 GHz, and three maximum beam directions of the antenna are ${\phi}_{max}=0^{\circ}$, ${\theta}_{max}=0^{\circ}$(Case 1), ${\phi}_{max}=230^{\circ}$, ${\theta}_{max}=40^{\circ}$(Case 2) and ${\phi}_{max}=130^{\circ}$, ${\theta}_{max}=40^{\circ}$ (Case 3). The peak gains of each case are 6.5 dBi(Case 1), 7.6 dBi(Case 2) and 7.8 dBi(Case 3). The half power beam width(HPBW) of each case is $86{\sim}104^{\circ}$, and the overall HPBW is $160^{\circ}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.6
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• pp.408-420
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• 2003

This paper describes a Delay Locked Loop (DLL) circuit having two advancements : 1) a dual loop operation for a wide lock-range and 2) programmable replica delays using antifuse circuitry and internal voltage generator for a post-package skew calibration. The dual loop operation uses information from the initial time-difference between reference clock and internal clock to select one of the differential internal loops. This increases the lock-range of the DLL to the lower frequency. In addition, incorporation with the programmable replica delay using antifuse circuitry and internal voltage generator allows for the elimination of skews between external clock and internal clock that occur from on and off-chip variations after the package process. The proposed DLL, fabricated on 0.16m process, operates over the wide range of 42MHz - 400MHz with 2.3v power supply. The measured results show 43psec peak-to-peak jitter and 4.71psec ms jitter consuming 52㎽ at 400MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.1
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• pp.1-10
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• 2013

In this paper, a broadband planar monopole antenna for multi-band services is proposed. The physical size of the proposed antenna is miniaturized by folding a rectangular loop. And a resonance point in the 3.9 GHz band is reduced by a coupling phenomenon with the central part of the T-shaped patch and the folded rectangular loop. In addition, the T-shaped patch is inserted to the rectangular shaped monopole antenna due to deriving the broadband frequency characteristics. The frequency characteristic is optimized by adjusting the gap and length of the folded rectangular loops and a transverse diameter of the T-shaped patch. The antenna dimensions including the ground plane are $40{\times}60{\times}1.6mm^3$. It is fabricated on the FR-4 substrate(${\epsilon}_r$=4.4) using a microstrip line of $50{\Omega}$ for impedance matching. In the measured result, the bandwidth corresponding to the VSWR of 2:1 is 162 MHz(815~977 MHz) and 2,530 MHz(1.43~3.96 GHz). For analyzing the human effect by the proposed antenna, 1 g and 10 g averaged SARs are simulated and measured. As the simulated results, 1 g-averaged SAR is 1.044 W/kg, and 10 g-averaged SAR is 0.718 W/kg. This result are satisfied by the SAR guidelines which are 1.6 W/kg(1 g-averaged) and 2.0 W/kg(10 g-averaged).

• Proceedings of the Korean Society of Soil and Groundwater Environment Conference
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• 2003.09a
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• pp.112-115
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• 2003

쓰레기매립장의 침출수 누출 탐지를 위한 물리탐사법은 침출수의 전기전도도를 대상으로 한 전기탐사법이 주로 적용되어 왔다. 이 연구는 제주도에 위치한 비위생매립지를 대상으로 주변 수리지질환경 파악을 위한 전기비저항 탐사와 더불어 매립장 경계부와 토양층을 통한 침출수 누출 영역을 효율적으로 규명하기 위하여 다중주파수를 이용한 소형루프 전자탐사를 병행하여 수행하였으며, 아울러 오염지역의 천부 지하수 유동 방향을 추정하기 위하여 침출수의 유동에 의해 발생될 수 있는 자연전위를 모니터링 하였다. 전기비저항 탐사 및 자연전위 모니터링 결과 매립지 주변을 통한 침출수의 누출 가능성은 거의 없는 것으로 나타났으며, 이는 주변 하천에서 정기적으로 실시한 수질 분석 결과와 일치된다. 또한 소형루프 전자탐사 자료에 대하여 공간 필터링 및 1차원 역산법을 적용한 결과 매립장 경계부의 위치 및 매립장 내부의 심도별 매립물에 의한 저비저항 이상대를 효과적으로 도출 할 수 있었다.